git.libre-soc.org Git - gem5.git/history

2015-10-12	Andreas Hansson	misc: Add explicit overrides and fix other clang >...	blob \| commitdiff \| raw
2015-10-12	Andreas Hansson	misc: Remove redundant compiler-specific defines	blob \| commitdiff \| raw \| diff to current
2015-07-07	Andreas Sandberg	sim: Refactor and simplify the drain API	blob \| commitdiff \| raw \| diff to current
2015-07-03	Wendy Elsasser	mem: Update DRAM command scheduler for bank groups	blob \| commitdiff \| raw \| diff to current
2015-07-03	Andreas Hansson	mem: Avoid DRAM write queue iteration for merging and...	blob \| commitdiff \| raw \| diff to current
2015-03-02	Andreas Hansson	mem: Split port retry for all different packet classes	blob \| commitdiff \| raw \| diff to current
2014-12-23	Andreas Hansson	mem: Ensure DRAM controller is idle when in atomic...	blob \| commitdiff \| raw \| diff to current
2014-12-23	Omar Naji	mem: Add rank-wise refresh to the DRAM controller	blob \| commitdiff \| raw \| diff to current
2014-10-20	Omar Naji	mem: Add DRAM device size and check against config	blob \| commitdiff \| raw \| diff to current
2014-07-29	Omar Naji	mem: DRAMPower integration for on-line DRAM power stats	blob \| commitdiff \| raw \| diff to current
2014-09-20	Wendy Elsasser	mem: Add DDR4 bank group timing	blob \| commitdiff \| raw \| diff to current
2014-09-20	Wendy Elsasser	mem: Add memory rank-to-rank delay	blob \| commitdiff \| raw \| diff to current
2014-08-26	Andreas Hansson	mem: Update DRAM controller comments	blob \| commitdiff \| raw \| diff to current
2014-08-26	Andreas Hansson	mem: Fix address interleaving bug in DRAM controller	blob \| commitdiff \| raw \| diff to current
2014-06-30	Andreas Hansson	mem: DRAMPower trace output	blob \| commitdiff \| raw \| diff to current
2014-06-30	Andreas Hansson	mem: Add bank and rank indices as fields to the DRAM...	blob \| commitdiff \| raw \| diff to current
2014-06-30	Andreas Hansson	mem: Extend DRAM row bits from 16 to 32 for larger...	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Add DRAM cycle time	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Simplify DRAM response scheduling	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Remove printing of DRAM params	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Add tRTP to the DRAM controller	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Merge DRAM latency calculation and bank state...	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Add tWR to DRAM activate and precharge constraints	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Add DRAM power states to the controller	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Ensure DRAM refresh respects timings	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Make DRAM read/write switching less conservative	blob \| commitdiff \| raw \| diff to current
2014-03-23	Andreas Hansson	mem: Track DRAM read/write switching and add hysteresis	blob \| commitdiff \| raw \| diff to current
2014-03-23	Andreas Hansson	mem: Rename SimpleDRAM to a more suitable DRAMCtrl	blob \| commitdiff \| raw \| diff to current

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