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mem: Fix DRAM controller to operate on its own address space
[gem5.git] / src / mem / dram_ctrl.hh
2019-10-29 Nikos Nikolerismem: Fix DRAM controller to operate on its own address... blob | commitdiff | raw
2019-09-30 Andreas Sandbergmem: Convert DRAM controller to new-style stats blob | commitdiff | raw | diff to current
2019-06-06 Matthew Porembamem: Option to toggle DRAM low-power states blob | commitdiff | raw | diff to current
2019-04-19 Daniel R. Carvalhomem: Make DRAMCtrl::decodeAddr const blob | commitdiff | raw | diff to current
2019-03-19 Gabe Blackarch, cpu, dev, gpu, mem, sim, python: start using... blob | commitdiff | raw | diff to current
2018-09-07 Matteo Andreozzimem: Make DRAMCtrl a QoS-aware Memory Controller blob | commitdiff | raw | diff to current
2018-05-18 Wendy Elsassermem: Add support for more flexible DRAM timing and... blob | commitdiff | raw | diff to current
2018-05-18 Wendy Elsassermem: Optimize self-refresh entry blob | commitdiff | raw | diff to current
2017-11-16 Radhika Jagtapext, mem: Pull DRAMPower SHA 90d6290 and rebase blob | commitdiff | raw | diff to current
2017-06-20 Sean Wilsonmem: Replace EventWrapper use with EventFunctionWrapper blob | commitdiff | raw | diff to current
2017-06-20 Sean Wilsonmem: Move the Rank construction logic to the Rank const... blob | commitdiff | raw | diff to current
2016-10-13 Wendy Elsassermem: Add DRAM low-power functionality blob | commitdiff | raw | diff to current
2016-10-13 Wendy Elsassermem: Add callback to compute stats prior to dump event blob | commitdiff | raw | diff to current
2016-10-13 Wendy Elsassermem: Modify drain to ensure banks and power are idled blob | commitdiff | raw | diff to current
2016-10-13 Wendy Elsassermem: Sort memory commands and update DRAMPower blob | commitdiff | raw | diff to current
2016-10-13 Omar Najimem: add DRAM powerdown timing blob | commitdiff | raw | diff to current
2016-07-01 Jason Lowe-Powermisc: merge with sytle checker fix blob | commitdiff | raw | diff to current
2016-07-01 Matthias Jungext: Update DRAMPower blob | commitdiff | raw | diff to current
2015-11-06 Andreas Hanssonmem: Unify delayed packet deletion blob | commitdiff | raw | diff to current
2015-10-12 Andreas Hanssonmisc: Add explicit overrides and fix other clang >... blob | commitdiff | raw | diff to current
2015-10-12 Andreas Hanssonmisc: Remove redundant compiler-specific defines blob | commitdiff | raw | diff to current
2015-07-07 Andreas Sandbergsim: Refactor and simplify the drain API blob | commitdiff | raw | diff to current
2015-07-03 Wendy Elsassermem: Update DRAM command scheduler for bank groups blob | commitdiff | raw | diff to current
2015-07-03 Andreas Hanssonmem: Avoid DRAM write queue iteration for merging and... blob | commitdiff | raw | diff to current
2015-03-02 Andreas Hanssonmem: Split port retry for all different packet classes blob | commitdiff | raw | diff to current
2014-12-23 Andreas Hanssonmem: Ensure DRAM controller is idle when in atomic... blob | commitdiff | raw | diff to current
2014-12-23 Omar Najimem: Add rank-wise refresh to the DRAM controller blob | commitdiff | raw | diff to current
2014-10-20 Omar Najimem: Add DRAM device size and check against config blob | commitdiff | raw | diff to current
2014-07-29 Omar Najimem: DRAMPower integration for on-line DRAM power stats blob | commitdiff | raw | diff to current
2014-09-20 Wendy Elsassermem: Add DDR4 bank group timing blob | commitdiff | raw | diff to current
2014-09-20 Wendy Elsassermem: Add memory rank-to-rank delay blob | commitdiff | raw | diff to current
2014-08-26 Andreas Hanssonmem: Update DRAM controller comments blob | commitdiff | raw | diff to current
2014-08-26 Andreas Hanssonmem: Fix address interleaving bug in DRAM controller blob | commitdiff | raw | diff to current
2014-06-30 Andreas Hanssonmem: DRAMPower trace output blob | commitdiff | raw | diff to current
2014-06-30 Andreas Hanssonmem: Add bank and rank indices as fields to the DRAM... blob | commitdiff | raw | diff to current
2014-06-30 Andreas Hanssonmem: Extend DRAM row bits from 16 to 32 for larger... blob | commitdiff | raw | diff to current
2014-05-09 Andreas Hanssonmem: Add DRAM cycle time blob | commitdiff | raw | diff to current
2014-05-09 Andreas Hanssonmem: Simplify DRAM response scheduling blob | commitdiff | raw | diff to current
2014-05-09 Andreas Hanssonmem: Remove printing of DRAM params blob | commitdiff | raw | diff to current
2014-05-09 Andreas Hanssonmem: Add tRTP to the DRAM controller blob | commitdiff | raw | diff to current
2014-05-09 Andreas Hanssonmem: Merge DRAM latency calculation and bank state... blob | commitdiff | raw | diff to current
2014-05-09 Andreas Hanssonmem: Add tWR to DRAM activate and precharge constraints blob | commitdiff | raw | diff to current
2014-05-09 Andreas Hanssonmem: Add DRAM power states to the controller blob | commitdiff | raw | diff to current
2014-05-09 Andreas Hanssonmem: Ensure DRAM refresh respects timings blob | commitdiff | raw | diff to current
2014-05-09 Andreas Hanssonmem: Make DRAM read/write switching less conservative blob | commitdiff | raw | diff to current
2014-03-23 Andreas Hanssonmem: Track DRAM read/write switching and add hysteresis blob | commitdiff | raw | diff to current
2014-03-23 Andreas Hanssonmem: Rename SimpleDRAM to a more suitable DRAMCtrl blob | commitdiff | raw | diff to current