git.libre-soc.org Git - gem5.git/history

2014-06-30	Andreas Hansson	mem: Add bank and rank indices as fields to the DRAM...	blob \| commitdiff \| raw
2014-06-30	Andreas Hansson	mem: Extend DRAM row bits from 16 to 32 for larger...	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Add DRAM cycle time	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Simplify DRAM response scheduling	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Remove printing of DRAM params	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Add tRTP to the DRAM controller	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Merge DRAM latency calculation and bank state...	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Add tWR to DRAM activate and precharge constraints	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Add DRAM power states to the controller	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Ensure DRAM refresh respects timings	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Make DRAM read/write switching less conservative	blob \| commitdiff \| raw \| diff to current
2014-03-23	Andreas Hansson	mem: Track DRAM read/write switching and add hysteresis	blob \| commitdiff \| raw \| diff to current
2014-03-23	Andreas Hansson	mem: Rename SimpleDRAM to a more suitable DRAMCtrl	blob \| commitdiff \| raw \| diff to current