git.libre-soc.org Git - gem5.git/history

2015-12-31	Andreas Hansson	mem: Make cache terminology easier to understand	blob \| commitdiff \| raw
2015-11-06	Andreas Hansson	mem: Align rules for sinking inhibited packets at the...	blob \| commitdiff \| raw \| diff to current
2015-11-06	Andreas Hansson	mem: Unify delayed packet deletion	blob \| commitdiff \| raw \| diff to current
2015-07-13	Andreas Hansson	mem: Updated DRAMSim2 wrapper to new drain API	blob \| commitdiff \| raw \| diff to current
2015-07-07	Andreas Sandberg	sim: Refactor and simplify the drain API	blob \| commitdiff \| raw \| diff to current
2015-07-07	Andreas Sandberg	sim: Make the drain state a global typed enum	blob \| commitdiff \| raw \| diff to current
2015-03-02	Marco Balboni	mem: Downstream components consumes new crossbar delays	blob \| commitdiff \| raw \| diff to current
2015-03-02	Andreas Hansson	mem: Split port retry for all different packet classes	blob \| commitdiff \| raw \| diff to current
2015-02-11	Marco Balboni	mem: Clarification of packet crossbar timings	blob \| commitdiff \| raw \| diff to current
2014-10-16	Andreas Hansson	mem: Dynamically determine page bytes in memory components	blob \| commitdiff \| raw \| diff to current
2014-09-20	Andreas Hansson	mem: Rename Bus to XBar to better reflect its behaviour	blob \| commitdiff \| raw \| diff to current
2014-08-26	Andreas Hansson	mem: Fix DRAMSim2 cycle check when restoring from check...	blob \| commitdiff \| raw \| diff to current
2014-02-18	Andreas Hansson	mem: Add a wrapped DRAMSim2 memory controller	blob \| commitdiff \| raw \| diff to current

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