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mem-cache: Add match functions to QueueEntry
[gem5.git]
/
src
/
mem
/
protocol
/
MI_example-cache.sm
2017-06-13
Nikos Nikoleris
ruby: Add support for address ranges in the directory
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2015-07-20
Tony Gutierrez
ruby: slicc: have a static MachineType
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2015-09-18
Nilay Vaish
ruby: print addresses in hex
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2015-09-16
Nilay Vaish
ruby: message buffer, timer table: significant changes
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2015-09-05
Nilay Vaish
ruby: call setMRU from L1 controllers, not from sequencer
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2015-09-05
Nilay Vaish
ruby: declare all protocol message buffers as parameters
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2015-08-19
Nilay Vaish
ruby: reverts to changeset: bf82f1f7b040
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2015-08-15
Nilay Vaish
ruby: call setMRU from L1 controllers, not from sequencer
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2015-08-15
Nilay Vaish
ruby: drop the [] notation for lookup function.
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2015-08-14
Nilay Vaish
ruby: replace Address by Addr
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2015-08-14
Nilay Vaish
ruby: rename variables Addr to addr
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2015-08-14
Joel Hestness
ruby: Protocol changes for SimObject MessageBuffers
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2014-11-06
Nilay Vaish
ruby: coherence protocols: remove data block from dirct...
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2014-09-01
Nilay Vaish
ruby: message buffers: significant changes
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2014-09-01
Nilay Vaish
ruby: slicc: change the way configurable members are...
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2014-05-23
Nilay Vaish
ruby: message buffer: drop dequeue_getDelayCycles()
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2014-04-08
Nilay Vaish
ruby: slicc: change enqueue statement
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2013-06-25
Nilay Vaish
ruby: profiler: lots of inter-related changes
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2013-06-24
Nilay Vaish
ruby: remove the three files related to profiling
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2013-06-18
Lena Olson
ruby: restrict Address to being a type and not a variab...
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2013-05-21
Nilay Vaish ext...
ruby: add stats to .sm files, remove cache profiler
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2013-02-11
Nilay Vaish
ruby: MI protocol: add a missing transition
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2013-02-11
Nilay Vaish
ruby: replaces Time with Cycles in many places
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2012-12-11
Nilay Vaish
ruby: change slicc to allow for constructor args
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2012-10-15
Nilay Vaish
ruby: improved support for functional accesses
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2012-10-02
Nilay Vaish
ruby: rename template_hack to template
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2012-09-30
Nilay Vaish
MI coherence protocol: add copyright notice
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2012-01-28
Gabe Black
Merge with the main repo.
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2012-01-23
Nilay Vaish
O3, Ruby: Forward invalidations from Ruby to O3 CPU
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2011-07-01
Brad Beckmann ext...
Ruby: Add support for functional accesses
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2011-06-08
Nilay Vaish
Ruby: Correctly set access permissions for directory...
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2011-05-20
Tushar Krishna
slicc: added vnet_type to MI_example
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2011-03-22
Nilay Vaish
Ruby: Remove CacheMsg class from SLICC
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2011-03-19
Nilay Vaish
Ruby: Convert CacheRequestType to RubyRequestType
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2011-03-18
Nilay Vaish
SLICC: Remove external_type for structures
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2011-02-24
Brad Beckmann
ruby: automate permission setting
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2011-01-18
Nilay Vaish
Change interface between coherence protocols and CacheM...
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2010-12-01
Nilay Vaish
ruby: Converted old ruby debug calls to M5 debug calls
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2010-08-20
Brad Beckmann
ruby: Reincarnated the responding machine profiling
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2010-03-22
Brad Beckmann
ruby: Reordered protocol buffers
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2010-01-30
Brad Beckmann
ruby: MI_example updates to use the new config system
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2010-01-22
Derek Hower
Automated merge with ssh://hg@m5sim.org/m5
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2010-01-19
Derek Hower
ruby: new atomics implementation
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2010-01-19
Derek Hower
merge
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2009-09-11
Derek Hower
merge
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2009-09-11
Derek Hower
merge
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2009-09-11
Derek Hower
Automated merge with ssh://hg@m5sim.org/m5
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2009-09-11
Derek Hower
protocol: made MI_example work with unordered networks
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2009-08-11
Brad Beckmann
merged Tushar's bug fix with public repository changes
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2009-08-05
Derek Hower
merge
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2009-08-04
Derek Hower
slicc: added MOESI_CMP_directory, DMA SequencerMsg...
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2009-07-20
Derek Hower
merge
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2009-07-20
Derek Hower
ruby: moved cache stats from Profiler to CacheMemory
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2009-07-06
Nathan Binkert
automerge
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2009-07-06
Nathan Binkert
ruby: Import the latest ruby changes from gems.
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2009-05-11
Korey Sewell
Merge Ruby Stuff
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2009-05-11
Nathan Binkert
ruby: Import ruby and slicc from GEMS
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