cpu: Fix broken squashAfter implementation in O3 CPU
[gem5.git] / src / mem /
2013-01-07 Andreas Sandbergmem: Remove the IIC replacement policy
2013-01-07 Andreas Hanssonsim: Fatal if a clocked object is set to have a clock...
2013-01-07 Andreas Hanssonmem: Merge ranges that are part of the conf table
2013-01-07 Andreas Hanssonmem: Add interleaving bits to the address ranges
2013-01-07 Andreas Hanssonbase: Simplify the AddrRangeMap by removing unused...
2013-01-07 Andreas Hanssonmem: Tidy up bus addr range debug messages
2013-01-07 Andreas Hanssonmem: Skip address mapper range checks to allow more...
2013-01-07 Andreas Hanssonbase: Encapsulate the underlying fields in AddrRange
2013-01-07 Andreas Hanssonmem: Remove the joining of neighbouring ranges
2013-01-07 Andreas Hanssonmem: Add tracing support in the communication monitor
2013-01-07 Andreas Hanssonmem: Add sanity check to packet queue size
2013-01-07 Andreas Hanssonruby: Fix missing cxx_header in Switch
2013-01-07 Andreas Hanssonmem: Fix a bug in the memory serialization file naming
2013-01-07 Ali Saidicache: add note about where conflicts are handled
2012-12-11 Nilay Vaishruby: add support for prefetching to MESI protocol
2012-12-11 Nilay Vaishruby: change slicc to allow for constructor args
2012-12-11 Nilay Vaishruby: add a prefetcher
2012-12-11 Nilay Vaishruby: add functions for computing next stride/page...
2012-11-16 Nilay Vaishsim: have a curTick per eventq
2012-11-10 Nilay Vaishruby: support functional accesses in garnet flexible...
2012-11-10 Nilay Vaishruby: bug in functionalRead, revert recent changes
2012-11-08 Andreas Hanssonmem: Fix DRAM draining to ensure write queue is empty
2012-11-02 Hamid Reza Khalegh... ruby: reset and dump stats along with reset of the...
2012-11-02 Ali Saidimem: fix use after free issue in memories until 4-phase...
2012-11-02 Andreas Sandbergmem: Add support for writing back and flushing caches
2012-11-02 Andreas Sandbergsim: Move the draining interface into a separate base...
2012-11-02 Andreas Sandbergsim: Include object header files in SWIG interfaces
2012-11-02 Dam SunwooARM: dump stats and process info on context switches
2012-10-31 Andreas Hanssonmem: Fix typo in port comments
2012-10-25 Andreas Hanssondev: Make default clock more reasonable for system...
2012-10-18 Nilay Vaishruby: functional access updates to network test protocol
2012-10-15 Nilay Vaishruby: improved support for functional accesses
2012-10-15 Nilay Vaish ruby: register multiple memory controllers
2012-10-15 Nilay Vaishruby: remove AbstractMemOrCache
2012-10-15 Nilay Vaishruby: allow function definition in slicc structs
2012-10-15 Nilay Vaishruby banked array: do away with event scheduling
2012-10-15 Nilay Vaishruby: reset timing after cache warm up
2012-10-15 Andreas HanssonMem: Fix incorrect logic in bus blocksize check
2012-10-15 Andreas HanssonPort: Add protocol-agnostic ports in the port hierarchy
2012-10-15 Andreas HanssonMem: Separate the host and guest views of memory backin...
2012-10-15 Andreas HanssonMem: Use deque instead of list for bus retries
2012-10-15 Andreas HanssonFix: Address a few minor issues identified by cppcheck
2012-10-15 Andreas HanssonMem: Use cycles to express cache-related latencies
2012-10-15 Andreas HanssonMem: Use range operations in bus in preparation for...
2012-10-11 Andreas HanssonMem: Determine bus block size during initialisation
2012-10-02 Nilay Vaishruby: makes some members non-static
2012-10-02 Nilay Vaishruby: changes to simple network
2012-10-02 Nilay Vaishruby: rename template_hack to template
2012-10-02 Nilay Vaishruby: remove unused code in protocols
2012-10-02 Nilay Vaishruby: remove some unused things in slicc
2012-10-02 Nilay Vaishruby: move functional access to ruby system
2012-09-30 Nilay VaishMI coherence protocol: add copyright notice
2012-09-25 Djordje KovacevicMEM: Put memory system document into doxygen
2012-09-25 Mrinmoy GhoshCache: add a response latency to the caches
2012-09-25 Ali Saidimem: Add a gasket that allows memory ranges to be re...
2012-09-23 Joel HestnessRubyPort and Sequencer: Fix draining
2012-09-21 Andreas HanssonDRAM: Introduce SimpleDRAM to capture a high-level...
2012-09-21 Andreas HanssonMem: Tidy up bus member variables types
2012-09-20 Anthony Gutierrezbus: removed outdated warn regarding 64 B block sizes
2012-09-19 Andreas HanssonMem: Remove the file parameter from AbstractMemory
2012-09-19 Andreas HanssonAddrRange: Transition from Range<T> to AddrRange
2012-09-19 Nilay Vaishruby: eliminate typedef integer_t
2012-09-19 Nilay Vaishruby: avoid using g_system_ptr for event scheduling
2012-09-18 Andreas HanssonMem: Add a maximum bandwidth to SimpleMemory
2012-09-14 Andreas Hanssonscons: Use c++0x with gcc >= 4.4 instead of 4.6
2012-09-12 Jason PowerRuby: Modify Scons so that we can put .sm files in...
2012-09-11 Andreas Hanssonclang: Fix issues identified by the clang static analyzer
2012-09-11 Lena OlsonCache: Split invalidateBlk up to seperate block vs...
2012-09-11 Nilay VaishRuby: Use uint32_t instead of uint32 everywhere
2012-09-11 Nilay VaishRuby: Use uint8_t instead of uint8 everywhere
2012-09-10 Nilay VaishRuby System: Convert to Clocked Object
2012-09-10 Nilay VaishRuby Slicc: remove the call to cin.get() function
2012-09-10 Marco ElverMem: Allow serializing of more than INT_MAX bytes
2012-09-07 Andreas HanssonParam: Transition to Cycles for relevant parameters
2012-09-06 Joel HestnessRuby Memory Controller: Fix clocking
2012-08-28 Jason PowerRuby: Correct DataBlock =operator
2012-08-28 Andreas HanssonClock: Add a Cycles wrapper class and use where applicable
2012-08-28 Andreas HanssonPort: Stricter port bind/unbind semantics
2012-08-27 Nilay VaishRuby: remove README.debugging and Decommissioning_note
2012-08-27 Nilay VaishRuby: Remove RubyEventQueue
2012-08-27 Nilay VaishRuby Memory Vector: Allow more than 4GB of memory
2012-08-25 Nilay VaishMESI Protocol: Correct the virtual network in profile...
2012-08-25 Nilay VaishMESI Coherence Protocol: Add copyright notice
2012-08-22 Andreas HanssonPacket: Remove NACKs from packet and its use in endpoints
2012-08-22 Andreas HanssonBridge: Remove NACKs in the bridge and unify with packe...
2012-08-22 Andreas HanssonPort: Extend the QueuedPort interface and use where...
2012-08-21 Andreas HanssonPacketQueue: Allow queuing in the same tick as desired...
2012-08-21 Andreas HanssonClock: Move the clock and related functions to ClockedO...
2012-08-19 Nilay VaishRuby Banked Array: add copyrights
2012-08-17 Jason PowerRuby: Add RubySystem parameter to MemoryControl
2012-08-15 Anthony GutierrezO3,ARM: fix some problems with drain/switchout function...
2012-08-10 Jason PowerRuby: Clean up topology changes
2012-08-06 Steve ReinhardtSETranslatingPortProxy: fix bug in tryReadString()
2012-08-01 Jason PowerRuby NetDest: add assert for bad element in netdest
2012-07-27 Anthony Gutierrezcache: don't allow dirty data in the i-cache
2012-07-23 Andreas HanssonBridge: Use EventWrapper instead of Event subclass...
2012-07-12 Andreas HanssonMem: Make SimpleMemory single ported
2012-07-12 Nilay VaishRuby: remove config information from ruby.stats
2012-07-12 Nilay VaishRuby: remove some unused stuff from SLICC files
2012-07-11 Brad Beckmannruby: improved DRAM reset comment
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