i965/nir/vec4: Prepare source and destination registers for ALU operations
[mesa.git] / src / mesa / drivers / dri / i965 / brw_ir_vec4.h
2015-06-09 Francisco Jerezi965: Define consistent interface to enable instruction...
2015-06-09 Francisco Jerezi965: Define consistent interface to enable instruction...
2015-06-09 Francisco Jerezi965: Define consistent interface to predicate an instr...
2015-05-04 Francisco Jerezi965: Perform basic optimizations on the BROADCAST...
2015-04-22 Jason Ekstrandi965: Add a devinfo field to backend_visitor and use...
2015-03-23 Francisco Jerezi965/vec4: Some more trivial swizzle clean-up.
2015-03-23 Francisco Jerezi965/vec4: Pass argument by reference to src_reg/dst_re...
2015-03-23 Francisco Jerezi965/vec4: Remove swizzle_for_size() in favour of brw_s...
2015-03-23 Francisco Jerezi965/vec4: Fix signedness of dst_reg::writemask.
2015-03-23 Francisco Jerezi965/vec4: Don't use GL types in the IR data structures.
2015-02-10 Francisco Jerezi965/vec4: Fix the scheduler to take into account reads...
2015-02-10 Francisco Jerezi965/vec4: Implement equals() method for dst_reg too.
2015-02-10 Francisco Jerezi965/vec4: Remove dependency of vec4_instruction on...
2015-02-10 Francisco Jerezi965: Move IR object definitions to separate header...