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change to use plain_data.fields
[nmigen-gf.git] / src / nmigen_gf / hdl / cldivrem.py
2022-08-16 Jacob Lifshaychange to use plain_data.fields master commit | commitdiff
2022-08-12 Jacob Lifshayswitch dataclass to plain_data commit | commitdiff
2022-05-06 Jacob Lifshaysplit step counter into clock and substep commit | commitdiff
2022-05-05 Jacob Lifshayremove now-unused EqualLeadingZeroCount commit | commitdiff
2022-05-05 Jacob Lifshayswitch to better CLDivRem algorithm commit | commitdiff
2022-05-05 Jacob Lifshayshrink signal widths commit | commitdiff
2022-05-05 Jacob Lifshayadd cldivrem_shifting as a more efficient algorithm commit | commitdiff
2022-05-04 Jacob Lifshayimplement CLDivRemFSMStage commit | commitdiff
2022-04-08 Jacob Lifshayclean up EqualLeadingZeroCount.elaborate commit | commitdiff
2022-04-08 Luke Kenneth Casso... move NOT into carrysum so that variable name commit | commitdiff
2022-04-07 Luke Kenneth Casso... remove addend1 and addend2 just add bothones and different. commit | commitdiff
2022-04-07 Luke Kenneth Casso... code-comments commit | commitdiff
2022-04-07 Luke Kenneth Casso... doh commit | commitdiff
2022-04-07 Luke Kenneth Casso... simplify code by removing for-loop and commenting why... commit | commitdiff
2022-04-07 Jacob Lifshayremove unused imports commit | commitdiff
2022-04-07 Jacob Lifshayswitch EqualLeadingZeroCount to use bitwise logic rathe... commit | commitdiff
2022-04-07 Jacob Lifshaychange reference algorithm to be more amenable to bitwi... commit | commitdiff
2022-04-05 Jacob Lifshayworking on adding CLDivRem commit | commitdiff