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bug 1034: yet again move crternlogi due to size of operands
[openpower-isa.git]
/
src
/
openpower
/
test
/
bitmanip
/
bitmanip_cases.py
2024-01-27
Luke Kenneth Casso...
bug 1034: yet again move crternlogi due to size of...
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2024-01-27
Luke Kenneth Casso...
bug 10344: had to move crfternlogi to TLI-Form
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2024-01-25
Luke Kenneth Casso...
bug 1034: add crbinlog and crternlogi, rename crbinlog...
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2024-01-20
Luke Kenneth Casso...
bug 1034: add crbinlog unit test, fix binlog test,...
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2024-01-20
Luke Kenneth Casso...
bug 1034: add crbinlog and binlog, unit test binlog...
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2024-01-17
Luke Kenneth Casso...
bug 1034: add crternlogi. involved adding a new CR...
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2023-12-07
Luke Kenneth Casso...
add gbbd (bmatflip) test case - just the one for now
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2023-09-12
Jacob Lifshay
remove grev, leaving unit tests for later use by grevlut
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2023-07-22
Luke Kenneth Casso...
shortened variable names,
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2023-07-22
Jacob Lifshay
add SVP64 test for byte reverse insns
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2023-07-20
Jacob Lifshay
add byte reverse instructions from PowerISA v3.1B
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2023-06-02
Dmitry Selyutin
pysvp64asm: integrate into insndb
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2022-08-13
Luke Kenneth Casso...
invalidate grev cases, replaced by grevlut
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2022-05-03
Jacob Lifshay
add Rc to ternlogi
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2022-01-18
Jacob Lifshay
grev[w][i][.] pseudo-code works
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2022-01-06
Jacob Lifshay
add stand-alone simulator bitmanip test
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2021-12-10
Jacob Lifshay
add ternlogi to SVP64Asm
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2021-12-10
Jacob Lifshay
change ternlogi to not have Rc field
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2021-12-09
Jacob Lifshay
make ternlogi tests run
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2021-12-09
Jacob Lifshay
rename ternaryi to ternlogi
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2021-11-17
Jacob Lifshay
add bitmanip_cases.py
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