sim: Only consider non-NULL elements in SimObjectVector.has_parent.
[gem5.git] / src / python / m5 /
2017-09-26 Gabe Blacksim: Only consider non-NULL elements in SimObjectVector...
2017-09-26 Gabe Blacksim: Add a set_parent to NullSimObject which does nothing.
2017-05-31 Nikos Nikolerispython: Fix unproxing of VectorParams
2017-05-24 Andreas Sandbergpython: Fix PyEvent reference counting bug
2017-05-22 Andreas Sandbergpython: Prevent Python wrappers from deleting SimObjects
2017-05-22 Andreas Sandbergpython: Fix weird memory issue in wrapped AddrRange...
2017-05-19 Andreas Sandbergpython: Remove unused readline import
2017-05-16 Andreas Sandbergpython: Add a helper function to create Python events
2017-05-15 Brandon Potterstyle: fix line lengths and include ordering
2017-05-09 Gabe Blackmisc: Add the --listener-loopback-only command line...
2017-05-09 Gabe Blackmisc: Expose the listener loopbackOnly function to...
2017-05-09 Andreas Sandbergpython: Fix debug flag listing regression
2017-05-02 Andreas Sandbergpython: Remove SWIG
2017-05-02 Andreas Sandbergpython: Use PyBind11 instead of SWIG for Python wrappers
2017-03-21 Andreas Sandbergpython: Automatically disable listeners in batch setups
2017-02-27 Andreas Sandbergpython: Add a generalized mechanism to configure stats
2017-01-27 Andreas Sandbergpython: Move native wrappers to the _m5 namespace
2017-01-03 Andreas Sandbergpython: Don't use Swig to cast stats
2017-01-03 Andreas Sandbergsim: Remove redundant export_method_cxx_predecls
2016-12-19 Andreas Sandbergpython: Export periodicStatDump
2016-09-15 Curtis Dunhambase: eliminate ipython warning
2016-09-14 Matt Porembabase: Output all AddrRange parameters to config.ini
2016-05-27 Akash Bagdiapower: Allow voltage to be configured via cmd line
2016-04-06 Sascha Bischoffmisc: Bail out of DVFS dot if we cannot resolve the...
2015-12-15 Sascha Bischoffmisc: Add secondary dot output for DVFS domains
2016-03-30 Andreas Sandbergstyle: Refactor the style checker as a Python package
2015-11-26 Andreas Sandbergsim: Add support for forking
2015-11-26 Andreas Sandbergsim: Add support for notifying Drainable objects of...
2016-02-13 Michael LeBeaneconfigs: add command-line option to stop debug output
2016-02-07 Steve Reinhardtstyle: remove trailing whitespace
2016-01-18 Steve Reinhardtsim: fix redundant --debug-start help string
2016-01-18 Steve Reinhardtsim: don't ignore SIG_TRAP
2015-12-01 Andreas Sandbergconfig: Fix broken SimObject listing
2015-11-22 Andrew Bardsleyconfig: Added missing types to JSON/INI Python reader
2015-10-07 Steve Reinhardtsim: print pid in output header
2015-09-30 Curtis Dunhambase: remove Trace::enabled flag
2015-07-07 Andreas Sandbergsim: Decouple draining from the SimObject hierarchy
2015-07-07 Andreas Sandbergsim: Move mem(Writeback|Invalidate) to SimObject
2015-07-07 Andreas Sandbergpython: Remove redundant drain when changing memory...
2015-07-07 Andreas Sandbergsim: Refactor the serialization base class
2015-03-23 Steve Reinhardtmisc: quote args in echoed command line
2015-02-03 Andreas Hanssonbase: Add XOR-based hashed address interleaving
2015-02-03 Geoffrey Blakeconfig: Fix typo in Float param
2014-12-02 Andreas Hanssonscons: Ensure dictionary iteration is sorted by key
2014-11-12 Andreas Hanssonsim: Sort SimObject descendants and ports
2014-10-16 Andreas Hanssonconfig: Add the ability to read a config file using...
2014-10-16 Andrew Bardsleyconfig: Add a --without-python option to build process
2014-10-11 Andrew Lukefahrsim: draining bug for fast-forwaring multiple cores stable_2014_12_14
2014-10-09 Andreas Hanssonconfig: Add Current as a parameter type
2014-09-20 Andreas Hanssonmem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 Andrew Bardsleyconfig: Cleanup .json config file generation
2014-09-09 Geoffrey Blakeconfig: Fix vectorparam command line parsing
2014-09-03 Geoffrey Blakeconfig: Add port splicing capability to PortRef class
2014-09-03 Mitch Hayengaconfig: Change parsing of Addr so hex values work from...
2014-08-10 Geoffrey Blakeconfig: Add hooks to enable new config sys
2014-05-09 Andrew Bardsleycpu: Add flag name printing to StaticInst
2014-05-09 Geoffrey Blakeconfig: Avoid generating a reference to myself for...
2014-05-09 Curtis Dunhamscons: Require SWIG >= 2.0.4 and remove vector typemaps
2014-04-23 Sascha Bischoffmisc: Proper type check and import for PortRef
2014-02-11 Curtis Dunhamstats: better error message for uninitialized statistic
2014-03-23 Stan Czerniawskimisc: Fix -q (quiet) flag
2014-01-24 Matt Horsnellbase: add support for probe points and common probes
2014-01-24 Andreas Hanssonconfig: Make the Clock a Tick parameter like Latency...
2014-01-04 Steve Reinhardtpython: provide better error message for wrapped C...
2014-01-04 Steve Reinhardtpython: don't die on assignment to cloned object
2013-12-03 Nilay Vaishsim: reset stats after startup
2013-11-25 Steve Reinhardt... sim: simulate with multiple threads and event queues
2013-11-14 Steve Reinhardttests: suppress output on switcheroo tests
2013-11-01 Andreas Hanssonsim: Clarify the difference between tracing and debugging
2013-10-31 Geoffrey Blakeconfig: Fix handling of parents for simobject vectors
2013-10-17 Geoffrey Blakeconfig: Fix ommission of number base in ethernet addres...
2013-10-17 Geoffrey Blakeconfig: Fix for port references generated multiple...
2013-09-18 Andreas Hanssonswig: Fix issue with circular import in 2.0.9/2.0.10
2013-09-04 Andreas Hanssonutil: Add ini string as tooltip info in dot output
2013-09-04 Andreas Hanssonutil: Add colours to the dot output
2013-09-04 Andreas Hanssonutil: Add class name to dot graph and output to svg
2013-08-19 Akash Bagdiapower: Add voltage domains to the clock domains
2013-07-18 Andreas Hanssonsim: Make MaxTick in Python match the one in C++
2013-06-27 Andreas Hanssonconfig: Remove Clock parameter multiplication
2013-02-19 Andreas Hanssonx86: Move APIC clock divider to Python
2013-02-15 Sascha Bischoffbase: Add warn() and inform() to m5.utils for use from...
2013-02-15 Andreas Sandbergsim: Add a system-global option to bypass caches
2013-02-15 Andreas Sandbergconfig: Move CPU handover logic to m5.switchCpus()
2013-02-10 Andreas Sandbergbase: Add support for newer versions of IPython
2013-02-10 Andreas Sandbergbase: Fix broken IPython argument handling
2013-01-07 Andreas Sandbergcpu: Introduce sanity checks when switching between...
2013-01-07 Andreas Hanssonmem: Add interleaving bits to the address ranges
2013-01-07 Andreas Hanssonconfig: Traverse lists when visiting children in all...
2012-11-02 Andreas Sandbergsim: Add drain methods to request additional cleanup...
2012-11-02 Andreas Sandbergsim: Add SWIG interface for Serializable
2012-11-02 Andreas Sandbergpython: Rename doDrain()->drain() and make it do the...
2012-11-02 Andreas Sandbergsim: Reuse the code to change memory mode.
2012-11-02 Andreas Sandbergsim: Move the draining interface into a separate base...
2012-11-02 Andreas Sandbergsim: Include object header files in SWIG interfaces
2012-11-02 Andreas SandbergPartly revert [4f54b0f229b5] and move draining to m5...
2012-10-15 Andreas HanssonParam: Fix proxy traversal to support chained proxies
2012-09-25 Sascha BischoffStatistics: Add a function to configure periodic stats...
2012-09-25 Andreas Sandbergsim: Move CPU-specific methods from SimObject to the...
2012-09-25 Andreas Sandbergsim: Remove SimObject::setMemoryMode
2012-09-19 Andreas HanssonAddrRange: Transition from Range<T> to AddrRange
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