o3: drop unused statistic wbPenalized and wbPenalizedRate
[gem5.git] / src / python / m5 /
2015-10-07 Steve Reinhardtsim: print pid in output header
2015-09-30 Curtis Dunhambase: remove Trace::enabled flag
2015-07-07 Andreas Sandbergsim: Decouple draining from the SimObject hierarchy
2015-07-07 Andreas Sandbergsim: Move mem(Writeback|Invalidate) to SimObject
2015-07-07 Andreas Sandbergpython: Remove redundant drain when changing memory...
2015-07-07 Andreas Sandbergsim: Refactor the serialization base class
2015-03-23 Steve Reinhardtmisc: quote args in echoed command line
2015-02-03 Andreas Hanssonbase: Add XOR-based hashed address interleaving
2015-02-03 Geoffrey Blakeconfig: Fix typo in Float param
2014-12-02 Andreas Hanssonscons: Ensure dictionary iteration is sorted by key
2014-11-12 Andreas Hanssonsim: Sort SimObject descendants and ports
2014-10-16 Andreas Hanssonconfig: Add the ability to read a config file using...
2014-10-16 Andrew Bardsleyconfig: Add a --without-python option to build process
2014-10-11 Andrew Lukefahrsim: draining bug for fast-forwaring multiple cores stable_2014_12_14
2014-10-09 Andreas Hanssonconfig: Add Current as a parameter type
2014-09-20 Andreas Hanssonmem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 Andrew Bardsleyconfig: Cleanup .json config file generation
2014-09-09 Geoffrey Blakeconfig: Fix vectorparam command line parsing
2014-09-03 Geoffrey Blakeconfig: Add port splicing capability to PortRef class
2014-09-03 Mitch Hayengaconfig: Change parsing of Addr so hex values work from...
2014-08-10 Geoffrey Blakeconfig: Add hooks to enable new config sys
2014-05-09 Andrew Bardsleycpu: Add flag name printing to StaticInst
2014-05-09 Geoffrey Blakeconfig: Avoid generating a reference to myself for...
2014-05-09 Curtis Dunhamscons: Require SWIG >= 2.0.4 and remove vector typemaps
2014-04-23 Sascha Bischoffmisc: Proper type check and import for PortRef
2014-02-11 Curtis Dunhamstats: better error message for uninitialized statistic
2014-03-23 Stan Czerniawskimisc: Fix -q (quiet) flag
2014-01-24 Matt Horsnellbase: add support for probe points and common probes
2014-01-24 Andreas Hanssonconfig: Make the Clock a Tick parameter like Latency...
2014-01-04 Steve Reinhardtpython: provide better error message for wrapped C...
2014-01-04 Steve Reinhardtpython: don't die on assignment to cloned object
2013-12-03 Nilay Vaishsim: reset stats after startup
2013-11-25 Steve Reinhardt... sim: simulate with multiple threads and event queues
2013-11-14 Steve Reinhardttests: suppress output on switcheroo tests
2013-11-01 Andreas Hanssonsim: Clarify the difference between tracing and debugging
2013-10-31 Geoffrey Blakeconfig: Fix handling of parents for simobject vectors
2013-10-17 Geoffrey Blakeconfig: Fix ommission of number base in ethernet addres...
2013-10-17 Geoffrey Blakeconfig: Fix for port references generated multiple...
2013-09-18 Andreas Hanssonswig: Fix issue with circular import in 2.0.9/2.0.10
2013-09-04 Andreas Hanssonutil: Add ini string as tooltip info in dot output
2013-09-04 Andreas Hanssonutil: Add colours to the dot output
2013-09-04 Andreas Hanssonutil: Add class name to dot graph and output to svg
2013-08-19 Akash Bagdiapower: Add voltage domains to the clock domains
2013-07-18 Andreas Hanssonsim: Make MaxTick in Python match the one in C++
2013-06-27 Andreas Hanssonconfig: Remove Clock parameter multiplication
2013-02-19 Andreas Hanssonx86: Move APIC clock divider to Python
2013-02-15 Sascha Bischoffbase: Add warn() and inform() to m5.utils for use from...
2013-02-15 Andreas Sandbergsim: Add a system-global option to bypass caches
2013-02-15 Andreas Sandbergconfig: Move CPU handover logic to m5.switchCpus()
2013-02-10 Andreas Sandbergbase: Add support for newer versions of IPython
2013-02-10 Andreas Sandbergbase: Fix broken IPython argument handling
2013-01-07 Andreas Sandbergcpu: Introduce sanity checks when switching between...
2013-01-07 Andreas Hanssonmem: Add interleaving bits to the address ranges
2013-01-07 Andreas Hanssonconfig: Traverse lists when visiting children in all...
2012-11-02 Andreas Sandbergsim: Add drain methods to request additional cleanup...
2012-11-02 Andreas Sandbergsim: Add SWIG interface for Serializable
2012-11-02 Andreas Sandbergpython: Rename doDrain()->drain() and make it do the...
2012-11-02 Andreas Sandbergsim: Reuse the code to change memory mode.
2012-11-02 Andreas Sandbergsim: Move the draining interface into a separate base...
2012-11-02 Andreas Sandbergsim: Include object header files in SWIG interfaces
2012-11-02 Andreas SandbergPartly revert [4f54b0f229b5] and move draining to m5...
2012-10-15 Andreas HanssonParam: Fix proxy traversal to support chained proxies
2012-09-25 Sascha BischoffStatistics: Add a function to configure periodic stats...
2012-09-25 Andreas Sandbergsim: Move CPU-specific methods from SimObject to the...
2012-09-25 Andreas Sandbergsim: Remove SimObject::setMemoryMode
2012-09-19 Andreas HanssonAddrRange: Transition from Range<T> to AddrRange
2012-09-19 Andreas HanssonAddrRange: Simplify AddrRange params Python hierarchy
2012-09-13 Joel HestnessStandard Switch: Drain the system before switching...
2012-09-07 Andreas Sandbergsim: Remove the unused SimObject::regFormulas method
2012-09-07 Andreas HanssonParam: Transition to Cycles for relevant parameters
2012-08-28 Andreas HanssonClock: Add a Cycles wrapper class and use where applicable
2012-07-11 Brad Beckmannruby: changes how Topologies are created
2012-06-05 Mitchell Hayengastats: Provide a mechanism to get a callback when stats...
2012-05-23 Andreas HanssonConfig: Use the attribute naming and include ports...
2012-05-23 Andreas HanssonConfig: Exit with fatal if a port is already connected
2012-05-10 Uri WienerDOT: improved dot-based system visualization
2012-05-10 Uri WienerDOT: fixed broken code for visualizing configuration...
2012-05-10 Ali Saidistats: track if the stats have been enabled and prevent...
2012-04-14 Andreas HanssonRegression: Add ANSI colours to highlight test status
2012-04-06 Brad Beckmannpython: added __nonzero__ function to SimObject Bool...
2012-04-05 Andreas HanssonPython: Make the All proxy traverse SimObject children...
2012-03-21 Andreas HanssonPython: Fix a conditional expression that requires...
2012-03-19 Andreas Hanssongcc: Clean-up of non-C++0x compliant code, first steps
2012-03-19 Andreas Hanssonscripts: Fix to ensure that port connection count is...
2012-02-29 Andreas HanssonSWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
2012-02-20 Steve ReinhardtSimObject: make get_config_as_dict() tolerate undefined...
2012-02-13 Andreas HanssonMEM: Pass the ports from Python to C++ using the Swig...
2012-02-13 Andreas HanssonMEM: Introduce the master/slave port roles in the Pytho...
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Koan-Sin Tanclang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-17 Andreas HanssonMEM: Removing the default port peer from Python ports
2012-01-10 Ali SaidiAutomated merge with ssh://repo.gem5.org/gem5
2012-01-10 Ali Saidiconfig: Fix json output for Python lt 2.6.
2012-01-10 Ali SaidiConfig: Fix issue with JSON output
2012-01-10 Prakash Ramrakhyanisim: Enable sampling of run-time for code-sections...
2012-01-10 Ali Saidiconfig: support outputing a pickle of the configuration...
2012-01-10 Andreas HanssonSWIG: Make gem5 compile and link with swig 2.0.4
2012-01-07 Gabe BlackMerge with main repository.
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