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construct an MSRSpec in PortInterfaceBase (not used yet)
[soc.git]
/
src
/
soc
/
experiment
/
pimem.py
2021-12-13
Luke Kenneth Casso...
construct an MSRSpec in PortInterfaceBase (not used...
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2021-12-13
Luke Kenneth Casso...
whoops wrong variable names
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2021-12-13
Luke Kenneth Casso...
TODO comments about using MSRspec
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2021-12-13
Luke Kenneth Casso...
change PortInterface naming to msr not msr_pr in set_wr...
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2021-12-13
Tobias Platen
add namedtuple proposed by lkcl in chat
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2021-12-13
Tobias Platen
add signals to port interface as descibed in bug 756
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2021-12-08
Luke Kenneth Casso...
add new PortInterfaceBase external_busy() option
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2021-12-04
Luke Kenneth Casso...
remove DAR from PortInterface (where is the data going...
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2021-12-03
Luke Kenneth Casso...
fix PortInterfaceBase
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2021-11-25
Tobias Platen
pimem: reset on exception
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2021-11-23
Tobias Platen
pimem changes for st exception handling
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2021-11-17
Tobias Platen
PortInterfaceBase: fix fast exception handling
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2021-11-15
Tobias Platen
report dar on exception + test case
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2021-11-11
Luke Kenneth Casso...
TODO, implement is_dcbz
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2021-10-08
Tobias Platen
more cleanup on pimem.py
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2021-10-08
Tobias Platen
an extra dcbz parameter in all six places
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2021-10-08
Luke Kenneth Casso...
have to remove dcbz from pimem.py entirely
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2021-10-08
Luke Kenneth Casso...
commented-out and disabled the set_dcbz_addr function...
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2021-10-08
Tobias Platen
dcbz: cleanup
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2021-10-08
Tobias Platen
dcbz symbol rename
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2021-10-08
Tobias Platen
PortInterfaceBase: add dcbz handling
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2021-10-03
Tobias Platen
more cleanup on pimem.py
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2021-10-03
Tobias Platen
an extra dcbz parameter in all six places
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2021-10-02
Luke Kenneth Casso...
have to remove dcbz from pimem.py entirely
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2021-10-02
Luke Kenneth Casso...
commented-out and disabled the set_dcbz_addr function...
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2021-10-02
Tobias Platen
dcbz: cleanup
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2021-10-02
Tobias Platen
dcbz symbol rename
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2021-10-02
Tobias Platen
PortInterfaceBase: add dcbz handling
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2021-05-11
Luke Kenneth Casso...
pass through MSR.PR through PortInterface, into LoadStore1
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2021-05-11
Luke Kenneth Casso...
add msr_pr bit in PortInterface
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2021-05-09
Luke Kenneth Casso...
update code-comments
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2021-05-09
Luke Kenneth Casso...
add misalign flag to PortInterfaceBase
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2021-05-04
Luke Kenneth Casso...
more rename of exception_o to exc_o, add convenience...
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2021-04-23
Luke Kenneth Casso...
move over to from openpower imports
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2020-10-07
Tobias Platen
connect mmu_done, ldst_error, cache_paradox
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2020-10-06
Tobias Platen
remove redunant signals
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2020-10-06
Luke Kenneth Casso...
update comments on pimem.py
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2020-10-06
Tobias Platen
test_mmu_dcache_pi.py
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2020-10-06
Luke Kenneth Casso...
move LDSTException to mem_types
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2020-10-06
Luke Kenneth Casso...
add LDSTException to PortInterface
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2020-09-15
Luke Kenneth Casso...
add extra "modes" to PortInterface
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2020-08-21
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-20
Tobias Platen
testcase refactoring
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2020-08-20
Tobias Platen
add new class TestCachedMemoryPortInterface
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2020-08-19
Luke Kenneth Casso...
more subtle interactions between wishbone bus when...
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2020-08-16
Luke Kenneth Casso...
fix LD/ST pimem issue with rising_edge detection
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2020-08-06
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
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2020-08-06
Luke Kenneth Casso...
fix LDST PortInterface FSM interaction
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2020-08-03
Luke Kenneth Casso...
https://bugs.libre-soc.org/show_bug.cgi?id=446
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2020-08-03
Tobias Platen
LDSTSplitter: report exception
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2020-07-22
Jacob Lifshay
Merge remote-tracking branch 'origin/master'
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2020-07-22
Jacob Lifshay
format code
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2020-07-02
Luke Kenneth Casso...
add bare wishbone option to TestIssuer, sort out ports
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2020-06-28
Luke Kenneth Casso...
got Pi2LSUI FSM working
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2020-06-28
Luke Kenneth Casso...
start new version of Pi2LSUI based on PortInterfaceBase
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2020-06-28
Luke Kenneth Casso...
pass addr/mask through to PortInterfaceBase rd/wr addr
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2020-06-28
Luke Kenneth Casso...
cleanup (remove unneeded imports)
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2020-06-28
Luke Kenneth Casso...
more code-shuffle for TestMemoryPortInterface
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2020-06-28
Luke Kenneth Casso...
more code-shuffle for TestMemoryPortInterface
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2020-06-28
Luke Kenneth Casso...
minor cleanup, put get/set rdport/wrport into function
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2020-06-28
Luke Kenneth Casso...
merge LDSTPort into TestMemoryPortInterface
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2020-06-28
Luke Kenneth Casso...
use PortInterface connect_port
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2020-06-28
Luke Kenneth Casso...
use PortInterface connect_port
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2020-06-27
Luke Kenneth Casso...
make PortInterface modules consistent with same API
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2020-06-26
Michael Nolan
Move tests for pimem to new file, add ability to test...
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2020-06-26
Luke Kenneth Casso...
halve the test memory size again
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2020-06-26
Luke Kenneth Casso...
shrink test memory size down to only 64 words
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2020-06-24
Michael Nolan
Revert "modify PortInterface so subfields include the...
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2020-06-23
Michael Nolan
modify PortInterface so subfields include the port...
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2020-06-23
Luke Kenneth Casso...
annoying error in latest nmigen
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2020-06-22
Luke Kenneth Casso...
simplified L0CacheBuffer down to a "PortInterface Arbiter"
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2020-06-22
Luke Kenneth Casso...
add TestMemoryPortInterface class which is designed...
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