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add attempt at mapping between PortInterface and LoadStoreUnitInterface
[soc.git]
/
src
/
soc
/
experiment
/
testmem.py
2020-06-16
Luke Kenneth Casso...
set up a TestIssuer class with a FSM for doing instruct...
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2020-06-16
Luke Kenneth Casso...
add ports to TestMemory
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2020-06-10
Luke Kenneth Casso...
got L0CacheBuffer shift/mask working on a preliminary...
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2020-06-09
Luke Kenneth Casso...
add convenience variables in TestMemory
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2020-04-24
Luke Kenneth Casso...
experimenting with ld/st comp unit
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2020-03-09
Luke Kenneth Casso...
disable transparent=False for now
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2020-03-09
Luke Kenneth Casso...
connect up LD to memory: set transparent mode to False.
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2020-03-09
Luke Kenneth Casso...
try adding test memory store to LDSTCompUnit
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