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add regression test for nonzero addis
[soc.git]
/
src
/
soc
/
fu
/
alu
/
output_stage.py
2020-07-12
Luke Kenneth Casso...
rename InternalOp to MicrOp
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2020-07-09
Luke Kenneth Casso...
also set so only if OE requires it
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2020-07-09
Luke Kenneth Casso...
whoops test gets copied 4 times on the If.
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2020-07-09
Luke Kenneth Casso...
ALU output stage, change logic slightly
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2020-07-09
Luke Kenneth Casso...
clarifying comments on setting xer_ov/so
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2020-06-08
Luke Kenneth Casso...
set only the SO bit as sticky, not the OV flags as...
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2020-06-06
Luke Kenneth Casso...
code-munge
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2020-05-28
Luke Kenneth Casso...
remove trick of not setting SO
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2020-05-27
Luke Kenneth Casso...
LogicalOutputData does not need XER.so
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2020-05-22
Luke Kenneth Casso...
split out Logical Input and Output stages to common...
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2020-05-20
Luke Kenneth Casso...
normalise XER regs carry/32 and SO
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2020-05-20
Luke Kenneth Casso...
convert alu output to use Data for XER and CR0
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2020-05-19
Michael Nolan
Handle carry out in alu
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2020-05-19
Luke Kenneth Casso...
32-bit testing of output for CR0 conditions
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2020-05-18
Luke Kenneth Casso...
mass-rename of modules to soc.fu.*
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2020-05-18
Luke Kenneth Casso...
rename pipe to fu
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