2021-05-04 |
Luke Kenneth Casso... | add printout showing exception output from FUs |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | more rename of exception_o to exc_o, add convenience... |
tree | commitdiff |
2021-04-30 |
Luke Kenneth Casso... | add a TestSRAM variant of LoadStore1, for being able... |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | fix import error |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | import from openpower.endian |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | use openpower.test.common |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move more files to openpower-isa |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move over to from openpower imports |
tree | commitdiff |
2021-04-20 |
Luke Kenneth Casso... | add enable MMU option to issuer_verilog.py |
tree | commitdiff |
2021-01-16 |
Tobias Platen | move microwatt_mmu bool variable to pspec |
tree | commitdiff |
2021-01-15 |
Tobias Platen | add microwatt_mmu boolean variable to core and compunits |
tree | commitdiff |
2021-01-10 |
Tobias Platen | add microwatt mmu config option to compunits.py |
tree | commitdiff |
2020-12-06 |
Cesar Strauss | Whitespace |
tree | commitdiff |
2020-12-06 |
Cesar Strauss | Update GTKWave documents to work with latest cxxsim |
tree | commitdiff |
2020-12-05 |
Cesar Strauss | Write a GTKWave document to investigate why the proof... |
tree | commitdiff |
2020-12-05 |
Cesar Strauss | Use the DummyALU regspec and its corresponding OpSubset |
tree | commitdiff |
2020-11-28 |
Cesar Strauss | Fix signal names: go/rel -> go_i/rel_o |
tree | commitdiff |
2020-10-12 |
Cole Poirier | fix ModuleNotFound/Import errors found when running... |
tree | commitdiff |
2020-10-06 |
Luke Kenneth Casso... | skip Decode2ToOperand from PowerDecodeSubset |
tree | commitdiff |
2020-09-26 |
Cesar Strauss | Convert a few more tests to be able to use cxxsim |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add MMU (commented out) |
tree | commitdiff |
2020-09-15 |
Luke Kenneth Casso... | instantiate MMU from AllFunctionUnits |
tree | commitdiff |
2020-09-07 |
Luke Kenneth Casso... | add pspec and opsubsetkls to CompUnits |
tree | commitdiff |
2020-09-02 |
Luke Kenneth Casso... | series of extensive modifications to fix long-standing... |
tree | commitdiff |
2020-08-29 |
Luke Kenneth Casso... | CR FXM becomes a full mask. |
tree | commitdiff |
2020-08-27 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2020-08-27 |
Luke Kenneth Casso... | sorting out shift_rot to use new output stage data... |
tree | commitdiff |
2020-08-26 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2020-08-26 |
Luke Kenneth Casso... | investigating div fsm and simulator bug |
tree | commitdiff |
2020-08-24 |
Luke Kenneth Casso... | make it easier to select FSM/Pipe DIV unit |
tree | commitdiff |
2020-08-24 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2020-08-22 |
Luke Kenneth Casso... | moved to div pipe temporarily in compunits |
tree | commitdiff |
2020-08-14 |
Luke Kenneth Casso... | fix test_compunit.py after moving decoder rdflags function |
tree | commitdiff |
2020-08-14 |
Luke Kenneth Casso... | sort out instruction stop/cancel when adding a new... |
tree | commitdiff |
2020-08-05 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2020-08-05 |
Luke Kenneth Casso... | add div FSM as default for test_issuer in verilog and... |
tree | commitdiff |
2020-08-04 |
Luke Kenneth Casso... | msr and pc moved to "state" in PowerDecode2 |
tree | commitdiff |
2020-07-31 |
Luke Kenneth Casso... | missed go_i/rel_o rename |
tree | commitdiff |
2020-07-29 |
Luke Kenneth Casso... | bit of a big change: add prefixes "cu_" to all CompUnit... |
tree | commitdiff |
2020-07-29 |
Jacob Lifshay | add __init__.py to all source directories |
tree | commitdiff |
2020-07-26 |
Luke Kenneth Casso... | argh add yet another latch to detect when LD/ST has... |
tree | commitdiff |
2020-07-26 |
Luke Kenneth Casso... | sigh, issue with detection/waiting for LD/ST CompUnit |
tree | commitdiff |
2020-07-26 |
Luke Kenneth Casso... | convert LDST test to accumulator style |
tree | commitdiff |
2020-07-26 |
Luke Kenneth Casso... | convert Branch test to accumulator style |
tree | commitdiff |
2020-07-26 |
Luke Kenneth Casso... | convert SPR test to accumulator style |
tree | commitdiff |
2020-07-26 |
Luke Kenneth Casso... | convert TRAP test to accumulator style |
tree | commitdiff |
2020-07-26 |
Luke Kenneth Casso... | convert CR test to accumulator style |
tree | commitdiff |
2020-07-26 |
Luke Kenneth Casso... | convert shift_rot test to new base accumulator style |
tree | commitdiff |
2020-07-26 |
Luke Kenneth Casso... | convert logical test case to new base class accumulator... |
tree | commitdiff |
2020-07-26 |
Luke Kenneth Casso... | convert ALU to new accumulator style |
tree | commitdiff |
2020-07-26 |
Luke Kenneth Casso... | run subtest, indentation getting too large, move to... |
tree | commitdiff |
2020-07-26 |
Luke Kenneth Casso... | get div compunit test running (use new way to accumulat... |
tree | commitdiff |
2020-07-25 |
Luke Kenneth Casso... | add div compunit test |
tree | commitdiff |
2020-07-25 |
Luke Kenneth Casso... | wait until pipeline indicates that its output is valid... |
tree | commitdiff |
2020-07-25 |
Luke Kenneth Casso... | move reset of rdmaskn to after "busy" |
tree | commitdiff |
2020-07-25 |
Luke Kenneth Casso... | comment LDST FunctionUnit |
tree | commitdiff |
2020-07-25 |
Luke Kenneth Casso... | going on a bit of a "naming" spree, this for Jean-Paul... |
tree | commitdiff |
2020-07-22 |
Jacob Lifshay | working on fsm |
tree | commitdiff |
2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
tree | commitdiff |
2020-07-22 |
Jacob Lifshay | format code |
tree | commitdiff |
2020-07-21 |
Luke Kenneth Casso... | interesting bug in test_compunit.py when there are... |
tree | commitdiff |
2020-07-21 |
Luke Kenneth Casso... | move cia and msr to trap input record |
tree | commitdiff |
2020-07-18 |
Luke Kenneth Casso... | missing conversion of DIV to Div |
tree | commitdiff |
2020-07-16 |
Luke Kenneth Casso... | get shiftrot compunit working |
tree | commitdiff |
2020-07-16 |
Luke Kenneth Casso... | get branch compunit working (missing bigendian arg) |
tree | commitdiff |
2020-07-16 |
Luke Kenneth Casso... | get trap compunit test working, adding bigendian and msr |
tree | commitdiff |
2020-07-12 |
Luke Kenneth Casso... | rename InternalOp to MicrOp |
tree | commitdiff |
2020-07-11 |
Luke Kenneth Casso... | add bigendian flag |
tree | commitdiff |
2020-07-11 |
Luke Kenneth Casso... | add endian |
tree | commitdiff |
2020-07-11 |
Luke Kenneth Casso... | sorting out bigendian/littleendian including in qemu |
tree | commitdiff |
2020-07-10 |
Luke Kenneth Casso... | re-add rc/oe back into LDST input record |
tree | commitdiff |
2020-07-10 |
Luke Kenneth Casso... | whew panic over, missed a bigendian argument in test_co... |
tree | commitdiff |
2020-07-08 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-07-07 |
Luke Kenneth Casso... | add in SPR test cases into test_issuer.py |
tree | commitdiff |
2020-07-06 |
Luke Kenneth Casso... | add mul compunit |
tree | commitdiff |
2020-07-06 |
Luke Kenneth Casso... | adding mtspr tests |
tree | commitdiff |
2020-07-06 |
Luke Kenneth Casso... | sort out initialisation of TstL0CacheBuffer in ldst... |
tree | commitdiff |
2020-07-05 |
Luke Kenneth Casso... | check trap compunit output properly |
tree | commitdiff |
2020-07-05 |
Luke Kenneth Casso... | big reorg on PowerDecoder2, actually Decode2Execute1Type |
tree | commitdiff |
2020-07-05 |
Luke Kenneth Casso... | sigh read and write xer detection, fix spr and trap... |
tree | commitdiff |
2020-07-05 |
Luke Kenneth Casso... | check spr1 in test spr compunit |
tree | commitdiff |
2020-07-05 |
Luke Kenneth Casso... | add first spr compunit test (not working yet) |
tree | commitdiff |
2020-07-05 |
Luke Kenneth Casso... | comment out SPR for now, needs SPR regfile |
tree | commitdiff |
2020-07-05 |
Luke Kenneth Casso... | add SPR compunit |
tree | commitdiff |
2020-07-04 |
Luke Kenneth Casso... | more updating spr1/spr2 to fast1/fast2 |
tree | commitdiff |
2020-07-04 |
Luke Kenneth Casso... | oops initialise Function Unit class with idx |
tree | commitdiff |
2020-07-04 |
Luke Kenneth Casso... | add first cookie-cut test_trap_compunit.py |
tree | commitdiff |
2020-07-02 |
Luke Kenneth Casso... | allow flexible selection of the types of ALUs |
tree | commitdiff |
2020-07-02 |
Luke Kenneth Casso... | fix unit tests due to change in using pspec |
tree | commitdiff |
2020-07-02 |
Luke Kenneth Casso... | allow ALU names to propagate through from FU to CompUni... |
tree | commitdiff |
2020-07-02 |
Luke Kenneth Casso... | name function unit ALUs |
tree | commitdiff |
2020-07-02 |
Luke Kenneth Casso... | comment out DIV unit for now |
tree | commitdiff |
2020-07-02 |
Luke Kenneth Casso... | add DIV function unit to compunits |
tree | commitdiff |
2020-07-02 |
Luke Kenneth Casso... | add trap function unit into compunits |
tree | commitdiff |
2020-07-01 |
Luke Kenneth Casso... | add in trap compunit |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | got Pi2LSUI FSM working |
tree | commitdiff |
2020-06-27 |
Luke Kenneth Casso... | make Memory accessible via TestSRAMBareLoadStoreUnit |
tree | commitdiff |
2020-06-27 |
Luke Kenneth Casso... | increase (double) address width in TstL0CacheBuffer |
tree | commitdiff |
2020-06-22 |
Luke Kenneth Casso... | simplified L0CacheBuffer down to a "PortInterface Arbiter" |
tree | commitdiff |
2020-06-18 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
next |