2021-05-11 |
Luke Kenneth Casso... | comment tidyup |
tree | commitdiff |
2021-05-11 |
Luke Kenneth Casso... | must also pass through instruction fault exception... |
tree | commitdiff |
2021-05-11 |
Luke Kenneth Casso... | whoops names changed in MMU FSM |
tree | commitdiff |
2021-05-11 |
Luke Kenneth Casso... | tidyup comments and remove LoadStore COMPLETE state |
tree | commitdiff |
2021-05-11 |
Luke Kenneth Casso... | cleanup on exception setting |
tree | commitdiff |
2021-05-11 |
Luke Kenneth Casso... | rename LoadStore1 data structures back to microwatt... |
tree | commitdiff |
2021-05-10 |
Luke Kenneth Casso... | add block for MMU activation to LoadStore1 |
tree | commitdiff |
2021-05-10 |
Luke Kenneth Casso... | move LoadStore1 d_validblip setting, and get MMU_LOOKUP... |
tree | commitdiff |
2021-05-10 |
Tobias Platen | style-wise: use ~self.instr_fault not self.instr_fault==0 |
tree | commitdiff |
2021-05-10 |
Tobias Platen | LoadStore1: add rules for MMU_LOOKUP |
tree | commitdiff |
2021-05-09 |
Luke Kenneth Casso... | add comments on translation of MMU_LOOKUP |
tree | commitdiff |
2021-05-09 |
Luke Kenneth Casso... | install MMU_LOOKUP vhdl to be translated to nmigen |
tree | commitdiff |
2021-05-09 |
Luke Kenneth Casso... | move (unused) ACK_WAIT code into FSM |
tree | commitdiff |
2021-05-09 |
Luke Kenneth Casso... | add comments in LoadStore1 |
tree | commitdiff |
2021-05-09 |
Luke Kenneth Casso... | remove invalid setting of d_in.valid from self.mmureq |
tree | commitdiff |
2021-05-09 |
Luke Kenneth Casso... | no SECOND_REQ |
tree | commitdiff |
2021-05-09 |
Luke Kenneth Casso... | remove SECOND_REQ |
tree | commitdiff |
2021-05-09 |
Tobias Platen | src/soc/fu/ldst/loadstore.py drive output d_in.valid |
tree | commitdiff |
2021-05-09 |
Tobias Platen | move skeleton to elaborate |
tree | commitdiff |
2021-05-09 |
Tobias Platen | src/soc/fu/ldst/loadstore.py: add skeleton for fsm |
tree | commitdiff |
2021-05-09 |
Luke Kenneth Casso... | add MMU bugtracker link |
tree | commitdiff |
2021-05-09 |
Luke Kenneth Casso... | update code-comments |
tree | commitdiff |
2021-05-09 |
Luke Kenneth Casso... | add in alignment exception capture/reporting in LoadStore1 |
tree | commitdiff |
2021-05-09 |
Luke Kenneth Casso... | preference is to create a temp variable for comb and... |
tree | commitdiff |
2021-05-09 |
Luke Kenneth Casso... | add misalign flag to PortInterfaceBase |
tree | commitdiff |
2021-05-08 |
Luke Kenneth Casso... | LoadStore1 tidyup |
tree | commitdiff |
2021-05-08 |
Luke Kenneth Casso... | transferring more over to LoadStore FSM |
tree | commitdiff |
2021-05-08 |
Luke Kenneth Casso... | start putting state info into LoadStore1, slowly puttin... |
tree | commitdiff |
2021-05-08 |
Luke Kenneth Casso... | add LoadStore State enum |
tree | commitdiff |
2021-05-08 |
Luke Kenneth Casso... | add bugreport link to mmu |
tree | commitdiff |
2021-05-07 |
Tobias Platen | fix 'sync' referenced before assignment in src/soc... |
tree | commitdiff |
2021-05-07 |
Luke Kenneth Casso... | start setting DSISR bits but commented out |
tree | commitdiff |
2021-05-07 |
Luke Kenneth Casso... | update comments and docstrings |
tree | commitdiff |
2021-05-07 |
Luke Kenneth Casso... | whoops, import error |
tree | commitdiff |
2021-05-07 |
Luke Kenneth Casso... | move LoadStore1 class to soc.fu.ldst.loadstore |
tree | commitdiff |
2021-05-07 |
Luke Kenneth Casso... | whoops was still copying output over in CommonOutputStage |
tree | commitdiff |
2021-05-07 |
Luke Kenneth Casso... | move dsisr and dar into LoadStore1 |
tree | commitdiff |
2021-05-07 |
Luke Kenneth Casso... | move zero-dest-pred in Common Output Stage to not copy... |
tree | commitdiff |
2021-05-06 |
Luke Kenneth Casso... | if zeroing is set, put zero into input or output as... |
tree | commitdiff |
2021-05-05 |
Tobias Platen | fix bug in mmu/fsm.py |
tree | commitdiff |
2021-05-05 |
Luke Kenneth Casso... | put sv_input_record_layout onto CompOpSubsetBase after all |
tree | commitdiff |
2021-05-05 |
Luke Kenneth Casso... | add SVP64 RM fields to ALU input record |
tree | commitdiff |
2021-05-04 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-05-04 |
Tobias Platen | implement MFSPR the same way as fu/spr/main_stage.py |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | add SVSTATE (SVSRR0) to TRAP pipeline |
tree | commitdiff |
2021-05-04 |
Tobias Platen | upate dsisr and dar using sync |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | adding fast3 SPR to Trap pipeline and unit test |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | add printout showing exception output from FUs |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | more rename of exception_o to exc_o, add convenience... |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | comments, and change name of LDSTCompUnit exception_o... |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | remove exception from data on FUBaseData, explicitly... |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | code-comments for LDSTCompUnit |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | add LDSTException class to LDSTOutputData |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | add option to add exception type to FUBaseData (pipe_data) |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | rename IntegerData to FUBaseData |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | comment out nc (nocache), it seems to actually work |
tree | commitdiff |
2021-05-03 |
Luke Kenneth Casso... | MMU: get store to activate only when data is available... |
tree | commitdiff |
2021-05-03 |
Luke Kenneth Casso... | disable the cache for now, whilst testing read/write... |
tree | commitdiff |
2021-05-02 |
Luke Kenneth Casso... | use Const to define bit-length when comparing top nibbl... |
tree | commitdiff |
2021-05-02 |
Luke Kenneth Casso... | mmu FSM store in dcache: only put data onto d_in on... |
tree | commitdiff |
2021-05-02 |
Luke Kenneth Casso... | return d_out.valid instead of always "ok" in MMU FSM |
tree | commitdiff |
2021-05-02 |
Luke Kenneth Casso... | HACK WARNING: disable d-cache on hard-coded address... |
tree | commitdiff |
2021-05-01 |
Luke Kenneth Casso... | store data in microwatt dcache goes in one cycle AFTER... |
tree | commitdiff |
2021-05-01 |
Luke Kenneth Casso... | only do dcache lookup for now |
tree | commitdiff |
2021-04-30 |
Luke Kenneth Casso... | debug and stop on mmu test_pipe_caller.py |
tree | commitdiff |
2021-04-30 |
Luke Kenneth Casso... | comments on dcache-to-mmu link |
tree | commitdiff |
2021-04-30 |
Luke Kenneth Casso... | add a TestSRAM variant of LoadStore1, for being able... |
tree | commitdiff |
2021-04-30 |
Luke Kenneth Casso... | hook up dcache wb_in/out to PortInterfaceBase Wishbone... |
tree | commitdiff |
2021-04-30 |
Luke Kenneth Casso... | set up LoadStore1 in ConfigMemoryPortInterface and... |
tree | commitdiff |
2021-04-29 |
Luke Kenneth Casso... | comment out adding mmu and dcache to pspec in MMU FSM |
tree | commitdiff |
2021-04-29 |
Luke Kenneth Casso... | move dcache into Loadstore1 |
tree | commitdiff |
2021-04-27 |
Luke Kenneth Casso... | return read data out from Loadstore1 only when valid |
tree | commitdiff |
2021-04-26 |
Luke Kenneth Casso... | hook up MSR into MMU (TODO, use a lot less bits) |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | fix import error |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | whitespace |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move logical tests to openpower.test |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | add trap test cases |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move SPR tests to openpower.test |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move branch test cases to openpower.test |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move LDST tests to openpower.test |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move mul tests to openpower.test |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move div tests to openpower.test |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move div tests to openpower.test |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move ALU test cases to openpower.test |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move MMU Testcase to openpower.test |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move CR test cases to openpower.test |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move shiftrot test cases to openpower.test |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | import from openpower.endian |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | use openpower.test.common |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move more files to openpower-isa |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | more openpower-isa conversion |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | correct migration of openpower-isa |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | more openpower import conversion |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move over to from openpower imports |
tree | commitdiff |
2021-04-21 |
Cesar Strauss | Add CR predication test case for TestIssuer |
tree | commitdiff |
2021-04-20 |
Luke Kenneth Casso... | add enable MMU option to issuer_verilog.py |
tree | commitdiff |
2021-04-20 |
Luke Kenneth Casso... | cannot pass in arguments to Core - must be done with... |
tree | commitdiff |
2021-04-10 |
Cesar Strauss | Add 1<<r3 test cases to TestIssuer |
tree | commitdiff |
2021-04-06 |
Cesar Strauss | Add a HDL test case, where we start at the middle of... |
tree | commitdiff |
2021-04-03 |
Cesar Strauss | Fix typo |
tree | commitdiff |
next |