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split out PowerDecode2 into PowerDecodeSubset
[soc.git]
/
src
/
soc
/
litex
/
2020-09-06
Luke Kenneth Casso...
minor code-munge on SPR-to-FAST mapping
tree
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commitdiff
2020-09-06
Luke Kenneth Casso...
redo generation of microwatt.v from litex
tree
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commitdiff
2020-09-05
Luke Kenneth Casso...
move GPIO IRQ to 15 to match microwatt modifications
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commitdiff
2020-09-05
Luke Kenneth Casso...
XICS addresses in words: divide by 4
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commitdiff
2020-09-05
Luke Kenneth Casso...
whoops, ICS in litex sim needs to be 0x1000 size region
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commitdiff
2020-09-05
Luke Kenneth Casso...
increase wishbone address width to 29 for xics and...
tree
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commitdiff
2020-09-05
Luke Kenneth Casso...
add simple GPIO wishbone bus to litex sim.py
tree
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commitdiff
2020-09-04
Luke Kenneth Casso...
reduce CSR data width to 8 as an experiment
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commitdiff
2020-09-04
Luke Kenneth Casso...
add UART reserved IRQ @ 0
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commitdiff
2020-09-04
Luke Kenneth Casso...
add XICS memory regions, shrink litex CSR memmap size...
tree
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commitdiff
2020-09-04
Luke Kenneth Casso...
adding XICS wb slave devices to litex sim
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commitdiff
2020-09-04
Luke Kenneth Casso...
adding option to include XICS external interrupts.
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commitdiff
2020-09-04
Luke Kenneth Casso...
add means to run hello_world.bin under simulation
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commitdiff
2020-09-03
Luke Kenneth Casso...
do more on dcache conversion
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commitdiff
2020-09-03
Luke Kenneth Casso...
testing microwatt 3.bin (2.bin ok)
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commitdiff
2020-09-02
Luke Kenneth Casso...
fix bug in cmpli (and cmplw)
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commitdiff
2020-09-02
Luke Kenneth Casso...
add bc ctr regression test when CTR=0 and CTR=1
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commitdiff
2020-08-31
Luke Kenneth Casso...
add XER to fastregs and "construct" it in mfspr/mtspr
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commitdiff
2020-08-30
Luke Kenneth Casso...
redo OP_CMP based on microwatt. L=1 had been ignored
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commitdiff
2020-08-29
Luke Kenneth Casso...
break down XER into flags
tree
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commitdiff
2020-08-29
Luke Kenneth Casso...
add XER read via DMI interface to sim.py
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commitdiff
2020-08-29
Luke Kenneth Casso...
investigating CR mtocrf / mfocrf
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commitdiff
2020-08-25
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
tree
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commitdiff
2020-08-25
Luke Kenneth Casso...
add way to capture CR from DMI in litex sim
tree
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commitdiff
2020-08-24
Luke Kenneth Casso...
argh, reading regfile over DMI was overlapped and corru...
tree
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commitdiff
2020-08-24
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
tree
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commitdiff
2020-08-23
Luke Kenneth Casso...
add algebraic ld tests lwax, lwaux
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commitdiff
2020-08-23
Luke Kenneth Casso...
add in DMI "stat" loop which monitors core "stopping"
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commitdiff
2020-08-23
Luke Kenneth Casso...
comment why litex sim mem map is altered
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commitdiff
2020-08-22
Luke Kenneth Casso...
load bios not 1.bin unit test
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commitdiff
2020-08-22
Luke Kenneth Casso...
add means to run microwatt test binaries
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commitdiff
2020-08-22
Luke Kenneth Casso...
investigating litex sdrinit function
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commitdiff
2020-08-21
Luke Kenneth Casso...
testing 64-bit wishbone bus after 32-bit *still* fails...
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commitdiff
2020-08-21
Luke Kenneth Casso...
get litex sim enabled with 32-bit wishbone bus
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commitdiff
2020-08-17
Luke Kenneth Casso...
move Mask to nmutil
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commitdiff
2020-08-17
Luke Kenneth Casso...
use longer memtest in litex sim
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commitdiff
2020-08-16
Luke Kenneth Casso...
attempting to track down bug in litex bios memtest
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commitdiff
2020-08-16
Luke Kenneth Casso...
limit debug reporting in litex sim to range of pc
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commitdiff
2020-08-15
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
tree
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commitdiff
2020-08-15
Luke Kenneth Casso...
thanks to daveshah, added simulation of dram
tree
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commitdiff
2020-08-05
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-08-05
Luke Kenneth Casso...
rename ibus/dbus (shorten)
tree
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commitdiff
2020-08-05
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
tree
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commitdiff
2020-08-05
Luke Kenneth Casso...
adding bus data width of 64 in litex sim doesnt work
tree
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commitdiff
2020-08-04
Luke Kenneth Casso...
cycle through INT regs, read and debug in litex sim
tree
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commitdiff
2020-08-04
Luke Kenneth Casso...
add DMI debug interface to libresoc litex sim
tree
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commitdiff
2020-08-04
Luke Kenneth Casso...
single-step and print out PC using DMI in litex sim
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commitdiff
2020-08-04
Luke Kenneth Casso...
get litex sim to kick off a "STEP" via the DMI interfac...
tree
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commitdiff
2020-08-04
Luke Kenneth Casso...
connect up a DMI FSM to litex sim
tree
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commitdiff
2020-08-04
Luke Kenneth Casso...
more remove wildcard imports
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commitdiff
2020-08-04
Luke Kenneth Casso...
do not use wildcard imports
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commitdiff
2020-08-04
Luke Kenneth Casso...
adding litex sim experimentation.
tree
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commitdiff
2020-07-23
Luke Kenneth Casso...
syntax error
tree
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commitdiff
2020-07-23
Luke Kenneth Casso...
support 32-bit mem width setting
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commitdiff
2020-07-23
Luke Kenneth Casso...
try SDRAM SDR
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commitdiff
2020-07-23
Luke Kenneth Casso...
try different MEMTEST_xxx sizes with 64 bit bus width
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commitdiff
2020-07-22
Jacob Lifshay
Merge remote-tracking branch 'origin/master'
tree
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commitdiff
2020-07-22
Luke Kenneth Casso...
re-add CRG (clock reset generator)
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commitdiff
2020-07-22
Luke Kenneth Casso...
add clock domain using snippet taken from random file
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commitdiff
2020-07-22
Luke Kenneth Casso...
cleanup in litex core.py
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commitdiff
2020-07-22
Luke Kenneth Casso...
update comments
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commitdiff
2020-07-22
Luke Kenneth Casso...
add dummy irq set/get
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commitdiff
2020-07-22
Luke Kenneth Casso...
add boot-helper.S etc from microwatt litex core
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commitdiff
2020-07-22
Luke Kenneth Casso...
missed import of Builder, set cpu_type to "None" tempor...
tree
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commitdiff
2020-07-22
Luke Kenneth Casso...
begin converting litex sim to libre-soc
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commitdiff
2020-07-22
Luke Kenneth Casso...
do not use wildcard import
tree
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commitdiff
2020-07-22
Luke Kenneth Casso...
start from vexriscv sim.py from
tree
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commitdiff
2020-07-22
Luke Kenneth Casso...
correct syntax error
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commitdiff
2020-07-22
Luke Kenneth Casso...
first version of litex core (to be submitted upstream...
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commitdiff