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make cxxsim optional and print warning
[soc.git]
/
src
/
soc
/
regfile
/
formal
/
2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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commitdiff
2020-07-04
Luke Kenneth Casso...
add gitignores
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2020-06-04
Luke Kenneth Casso...
use copy of FHDLTestCase
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2020-06-01
Michael Nolan
Add proof for RegFile
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2020-06-01
Michael Nolan
Add proof for RegFileArray
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2020-06-01
Michael Nolan
Have regfile use AnySeq instead of AnyConst
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2020-06-01
Michael Nolan
Enable k-induction for register file proof
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2020-06-01
Michael Nolan
That was weird. For some reason it wasn't generating...
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2020-06-01
Michael Nolan
Full BMC proof of Register
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2020-06-01
Michael Nolan
Begin rewrite of proof_regfile.py
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2020-05-28
Luke Kenneth Casso...
messing about with proof_regfile.py
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2020-05-28
colepoirier
Added Initial() synchronous check with draft truth
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2020-05-28
Luke Kenneth Casso...
hmm....
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2020-05-28
colepoirier
Add sync Assert for _wrports 'wen' signal in proof_regf...
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2020-05-27
Luke Kenneth Casso...
do not use range(0, x) - just range(x)
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2020-05-27
colepoirier
Derive proof_regfile Driver from regfile.Register(...
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2020-05-27
colepoirier
Fix indentation of regfile/formal/proof_regfile.py
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2020-05-27
colepoirier
First commit of proof of regfile, not working yet
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