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starting to add SVP64 register EXTRA-read and isvec to ISACaller
[soc.git]
/
src
/
soc
/
regfile
/
util.py
2020-09-06
Luke Kenneth Casso...
add unit test for slow SPRs (SPRG0/1)
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2020-09-06
Luke Kenneth Casso...
minor code-munge on SPR-to-FAST mapping
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2020-07-08
Luke Kenneth Casso...
adding in ALU test back in, debugging SPR setup
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2020-07-08
Luke Kenneth Casso...
sorting out setting of XER
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2020-07-08
Luke Kenneth Casso...
add spr to fast reg converter
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-04
Luke Kenneth Casso...
debugging decoding of SPRs (fast)
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2020-06-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-06-02
Luke Kenneth Casso...
decode fast spr for OP_BCREG CTR, TAR and LR
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