2021-04-30 |
Luke Kenneth Casso... | add a TestSRAM variant of LoadStore1, for being able... |
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2021-04-30 |
Luke Kenneth Casso... | set up LoadStore1 in ConfigMemoryPortInterface and... |
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2021-04-23 |
Luke Kenneth Casso... | move over to from openpower imports |
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2021-04-18 |
Luke Kenneth Casso... | core_stopped_i unused: remove |
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2021-03-30 |
Alain D D Williams | Merge branch 'master' of git.libre-soc.org:soc |
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2021-03-28 |
Luke Kenneth Casso... | svp64-enable passed through to PowerDecoderSubsets... |
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2021-03-28 |
Luke Kenneth Casso... | add option to reduce number of regfile ports (get DFFs... |
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2021-03-28 |
Luke Kenneth Casso... | reduce number of regfile ports |
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2021-03-28 |
Luke Kenneth Casso... | reduce regfile port usage on non-svp64 |
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2021-03-11 |
Luke Kenneth Casso... | add link of RA_OR_ZERO SVP64 detection |
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2021-02-04 |
Tobias Platen | pass SPR MicroOp to MMU function unit |
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2021-01-16 |
Tobias Platen | move microwatt_mmu bool variable to pspec |
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2021-01-15 |
Tobias Platen | add microwatt_mmu boolean variable to core and compunits |
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2020-10-15 |
Luke Kenneth Casso... | sorting out missing clock somewhere |
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2020-10-07 |
Luke Kenneth Casso... | reorder / reorganise reset signals slightly |
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2020-10-06 |
Luke Kenneth Casso... | skip Decode2ToOperand from PowerDecodeSubset |
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2020-09-28 |
Luke Kenneth Casso... | missing pspec |
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2020-09-28 |
Luke Kenneth Casso... | add "nocore" option to build verilog |
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2020-09-22 |
Luke Kenneth Casso... | add MMU (commented out) |
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2020-09-08 |
Luke Kenneth Casso... | create a special subset of Decoder Record for storing... |
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2020-09-08 |
Luke Kenneth Casso... | give Decode2Execute1Type in core a name |
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2020-09-08 |
Luke Kenneth Casso... | pass in CoreState to PowerDecoder rather than eq a... |
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2020-09-07 |
Luke Kenneth Casso... | use PowerDecoderSubsets for FUs, except for TRAP which... |
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2020-09-07 |
Luke Kenneth Casso... | add per-FU PowerDecoders. should now be subsettable |
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2020-09-05 |
Luke Kenneth Casso... | connect XICS core irq to Decode2 eint |
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2020-09-04 |
Luke Kenneth Casso... | adding option to include XICS external interrupts. |
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2020-08-15 |
Luke Kenneth Casso... | rather big change to interaction between regfile and... |
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2020-08-14 |
Luke Kenneth Casso... | move instruction decoder out of core |
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2020-08-14 |
Luke Kenneth Casso... | move regspec / rdflag decoding functions out of PowerDe... |
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2020-08-14 |
Luke Kenneth Casso... | put multi-ports back (for read) on int and fast regfiles |
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2020-08-13 |
Luke Kenneth Casso... | sync on read of regfile ports |
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2020-08-13 |
Luke Kenneth Casso... | sigh. convert INT regfile to binary addressing |
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2020-08-11 |
Luke Kenneth Casso... | sigh, remove yet another int regfile read port |
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2020-08-11 |
Luke Kenneth Casso... | massive reduction in gate count by using alternative... |
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2020-08-11 |
Luke Kenneth Casso... | reduce regfile port usage for INT and FAST |
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2020-08-11 |
Luke Kenneth Casso... | prepare write ports to be shared |
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2020-08-11 |
Luke Kenneth Casso... | move write regfile picker creation to new function |
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2020-08-11 |
Luke Kenneth Casso... | reducing regfile port usage by sharing read ports |
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2020-08-10 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-09 |
Luke Kenneth Casso... | write pulse in issuer |
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2020-08-04 |
Luke Kenneth Casso... | allow instruction to run if initiated whilst "stopped... |
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2020-08-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-08-03 |
Luke Kenneth Casso... | change over to DMI debug start/stop interface |
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2020-07-29 |
Luke Kenneth Casso... | bit of a big change: add prefixes "cu_" to all CompUnit... |
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2020-07-23 |
Luke Kenneth Casso... | begin core in running state |
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2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
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2020-07-22 |
Jacob Lifshay | format code |
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2020-07-19 |
Luke Kenneth Casso... | do not start core in terminated mode |
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2020-07-12 |
Luke Kenneth Casso... | rename InternalOp to MicrOp |
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2020-07-12 |
Luke Kenneth Casso... | code-morph on core connect_instruction |
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2020-07-11 |
Luke Kenneth Casso... | sort out core write latching: gate by busy, and use... |
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2020-07-11 |
Luke Kenneth Casso... | * clarifying core function unit enable |
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2020-07-08 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-07-07 |
Luke Kenneth Casso... | sort-of got binary execution test working |
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2020-07-07 |
Luke Kenneth Casso... | ordering of tests for OP_ATTN needed shuffling. seems... |
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2020-07-07 |
Luke Kenneth Casso... | debugging termination / OP_ATTN |
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2020-07-07 |
Luke Kenneth Casso... | add core start/stop capability, and OP_ATTN support |
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2020-07-05 |
Luke Kenneth Casso... | big reorg on PowerDecoder2, actually Decode2Execute1Type |
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2020-07-05 |
Luke Kenneth Casso... | move valid signal out of Decode2ToExecute1Type and... |
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2020-07-02 |
Luke Kenneth Casso... | allow flexible selection of the types of ALUs |
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2020-07-02 |
Luke Kenneth Casso... | add bare wishbone option to TestIssuer, sort out ports |
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2020-07-02 |
Luke Kenneth Casso... | use single-arg pspec for TestIssuer and Core |
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2020-06-27 |
Luke Kenneth Casso... | make PortInterface modules consistent with same API |
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2020-06-23 |
Luke Kenneth Casso... | TstL0CacheBuffer returns array of ports differently now |
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2020-06-18 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-06-18 |
Luke Kenneth Casso... | whoops generate core ilang not TestIssuer |
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2020-06-17 |
Luke Kenneth Casso... | split out TestIssuer into separate module |
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2020-06-17 |
Luke Kenneth Casso... | got test_issuer FSM operating. bit of a hack |
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2020-06-17 |
Luke Kenneth Casso... | debugging test_issuer, getting FSM working |
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2020-06-16 |
Luke Kenneth Casso... | reduce instruction depth to 6 bits in TestIssuer |
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2020-06-16 |
Luke Kenneth Casso... | hack LD/ST ad/st together, allow PC to be set externally |
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2020-06-16 |
Luke Kenneth Casso... | set up a TestIssuer class with a FSM for doing instruct... |
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2020-06-16 |
Luke Kenneth Casso... | add beginnings of TestIssuer class, to issue instructio... |
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2020-06-16 |
Luke Kenneth Casso... | weird: adding TestMemory with no port causes nmigen... |
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2020-06-16 |
Luke Kenneth Casso... | refer to signals directly in Test Core |
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2020-06-16 |
Luke Kenneth Casso... | add test instruction memory SRAM |
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2020-06-15 |
Luke Kenneth Casso... | whoops LDSTCompUnit was identified as a Function.ALU... |
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2020-06-15 |
Luke Kenneth Casso... | add in TstL0CacheBuffer but disable temporarily |
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2020-06-10 |
Luke Kenneth Casso... | code-morph regspecmap functions, split into separate... |
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2020-06-05 |
Luke Kenneth Casso... | name regfile ports by name not numerical position |
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2020-06-05 |
Luke Kenneth Casso... | whoops connecting up CR in wrong order. fixing with... |
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2020-06-04 |
Luke Kenneth Casso... | whoops, docstring indentation |
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2020-06-04 |
Luke Kenneth Casso... | add docstrings for read/write port connection |
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2020-06-04 |
Luke Kenneth Casso... | move core code into separate functions, for clarity |
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2020-06-04 |
Luke Kenneth Casso... | oops forgot to switch write-enable off |
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2020-06-04 |
Luke Kenneth Casso... | hmmm sync-delay wport write and wen |
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2020-06-04 |
Luke Kenneth Casso... | comment out wrflag as it should already be in the fu... |
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2020-06-04 |
Luke Kenneth Casso... | sync onto fu.go_wr_i otherwise a loop occurs |
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2020-06-04 |
Luke Kenneth Casso... | add rdmask and issue/busy setting |
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2020-06-04 |
Luke Kenneth Casso... | connect up write-ports from Regfiles to FUs |
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2020-06-04 |
Luke Kenneth Casso... | update docstring on simple/core.py |
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2020-06-04 |
Luke Kenneth Casso... | move regfile/spec organiser to separate function |
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2020-06-04 |
Luke Kenneth Casso... | collate fu-enable signals |
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2020-06-04 |
Luke Kenneth Casso... | connect up Function Unit operand subsets |
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2020-06-03 |
Luke Kenneth Casso... | forgot to add in rdflag enable |
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2020-06-03 |
Luke Kenneth Casso... | whoops, regfiles are uppercase |
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2020-06-03 |
Luke Kenneth Casso... | whoops needed a bit of a reorg of the data structure... |
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2020-06-03 |
Luke Kenneth Casso... | hmmm got naming wrong in regfile-fu connectivity |
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2020-06-03 |
Luke Kenneth Casso... | whoops names of regfiles are lower-case |
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2020-06-03 |
Luke Kenneth Casso... | munge/redirect the regfile port based on the naming |
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