2021-12-01 |
Luke Kenneth Casso... | stack of changes to MultiCompUnit to speed it up |
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2021-12-01 |
Luke Kenneth Casso... | FunctionUnitBaseMulti which derives from ReservationSta... |
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2021-11-30 |
Luke Kenneth Casso... | start allocating more FUs (more ReservationStations) |
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2021-11-30 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-11-30 |
Luke Kenneth Casso... | add LogicalTestCases back in to test_core.py (pass) |
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2021-11-30 |
Luke Kenneth Casso... | let PowerDecode2 decide which operand class to use... |
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2021-11-30 |
Luke Kenneth Casso... | allow busy to settle before checking state in test_core.py |
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2021-11-30 |
Luke Kenneth Casso... | only check regs right at the end in test_core.py overla... |
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2021-11-30 |
Luke Kenneth Casso... | move sim call before core run in test_core.py |
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2021-11-30 |
Luke Kenneth Casso... | getting formerly unused test_core.py operational |
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2021-11-10 |
Luke Kenneth Casso... | allow MSR to be set in StateRegs in test_core.py |
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2021-09-25 |
Las Safin | Merge remote-tracking branch 'upstream/master' into pr |
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2021-09-22 |
Luke Kenneth Casso... | alter setup_tst_memory to take a test.mem rather than... |
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2021-09-22 |
Luke Kenneth Casso... | whoops forgot to do with self.subTest() |
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2021-09-21 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-09-21 |
klehman | changed over to use state mem compare |
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2021-09-16 |
Luke Kenneth Casso... | moving teststate_check_regs written by klehman into... |
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2021-09-15 |
isengaara | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-09-14 |
Luke Kenneth Casso... | convert to using TestState and State after moving to... |
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2021-09-12 |
Luke Kenneth Casso... | code comments |
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2021-09-12 |
Luke Kenneth Casso... | create new function teststate_check_regs which is calle... |
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2021-09-12 |
klehman | changes to utilize full teststate class |
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2021-09-10 |
klehman | changes made to utilize teststate class |
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2021-09-07 |
Luke Kenneth Casso... | fun fixing of get_core_hdl_regs, "yield from" |
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2021-09-07 |
Luke Kenneth Casso... | move functions to above where they are called |
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2021-09-07 |
klehman | breakout of register collection and compare |
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2021-09-07 |
Cesar Strauss | Fix typo. |
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2021-09-07 |
Luke Kenneth Casso... | add TODO code-comments |
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2021-09-07 |
Luke Kenneth Casso... | whitespace, add bug ref number to test API |
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2021-08-29 |
Luke Kenneth Casso... | unnecessary signal rename ivalid_i to ii_valid (reverting) |
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2021-08-24 |
Luke Kenneth Casso... | replace data_o with o_data and data_i with i_data as... |
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2021-08-24 |
Luke Kenneth Casso... | big rename, global/search/replace of ready_o with o_rea... |
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2021-08-01 |
Jonathan Neuschäfer | soc.simple.test: Rename setup_test_memory to avoid... |
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2021-05-01 |
Luke Kenneth Casso... | use new AllFunctionUnits.get_fu function |
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2021-05-01 |
Luke Kenneth Casso... | use SPRreduced to match PowerDecoder2 |
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2021-04-30 |
Luke Kenneth Casso... | https://bugs.libre-soc.org/show_bug.cgi?id=635 |
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2021-04-30 |
Luke Kenneth Casso... | better reporting on gpr comparisons |
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2021-04-23 |
Luke Kenneth Casso... | error in setting fast regs test values |
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2021-04-23 |
Luke Kenneth Casso... | move more files to openpower-isa |
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2021-04-23 |
Luke Kenneth Casso... | move over to from openpower imports |
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2021-04-21 |
Tobias Platen | testcase: pass PRTBL to mmu |
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2021-03-30 |
Alain D D Williams | Merge branch 'master' of git.libre-soc.org:soc |
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2021-03-28 |
Luke Kenneth Casso... | rather invasive reduction of SPR regfile size |
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2021-03-02 |
Luke Kenneth Casso... | sort out SPR setting in MMU |
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2021-02-16 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-02-15 |
Cesar Strauss | Simplify obtaining the PC from the register file |
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2021-02-15 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-02-13 |
Cesar Strauss | Check the PC value at the end of each instruction |
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2021-01-18 |
Tobias Platen | uncomment #FIXME in unit_test |
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2021-01-08 |
Tobias Platen | fix broken testcase for simple core |
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2020-08-15 |
Luke Kenneth Casso... | rather big change to interaction between regfile and... |
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2020-08-14 |
Luke Kenneth Casso... | move instruction decoder out of core |
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2020-08-13 |
Luke Kenneth Casso... | sigh. convert INT regfile to binary addressing |
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2020-08-03 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-08-03 |
Luke Kenneth Casso... | change over to DMI debug start/stop interface |
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2020-07-22 |
Jacob Lifshay | Merge remote-tracking branch 'origin/master' |
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2020-07-22 |
Jacob Lifshay | format code |
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2020-07-11 |
Luke Kenneth Casso... | fix spr setting, set endianness |
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2020-07-08 |
Luke Kenneth Casso... | resolving old and new behaviour for lookup of SPRs |
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2020-07-08 |
Luke Kenneth Casso... | resolving old and new behaviour for lookup of SPRs |
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2020-07-08 |
Luke Kenneth Casso... | adding in ALU test back in, debugging SPR setup |
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2020-07-08 |
Luke Kenneth Casso... | sorting out setting of XER |
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2020-07-08 |
Jacob Lifshay | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-07-07 |
Luke Kenneth Casso... | ordering of tests for OP_ATTN needed shuffling. seems... |
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2020-07-07 |
Luke Kenneth Casso... | debugging termination (OP_ATTN) |
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2020-07-07 |
Luke Kenneth Casso... | debugging termination / OP_ATTN |
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2020-07-05 |
Luke Kenneth Casso... | big reorg on PowerDecoder2, actually Decode2Execute1Type |
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2020-07-04 |
Luke Kenneth Casso... | add pspec to test_core.py |
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2020-07-04 |
Luke Kenneth Casso... | add pspec to test_core.py |
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2020-06-17 |
Luke Kenneth Casso... | enable all tests again in test_core.py and test_issuer.py |
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2020-06-17 |
Luke Kenneth Casso... | debugging test_issuer, getting FSM working |
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2020-06-16 |
Luke Kenneth Casso... | reduce instruction depth to 6 bits in TestIssuer |
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2020-06-16 |
Luke Kenneth Casso... | move debug statements to check function |
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2020-06-16 |
Luke Kenneth Casso... | move check regs in simple core to separate function |
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2020-06-16 |
Luke Kenneth Casso... | move test core reg set up into separate function |
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2020-06-16 |
Luke Kenneth Casso... | add beginnings of TestIssuer class, to issue instructio... |
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2020-06-16 |
Luke Kenneth Casso... | refer to signals directly in Test Core |
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2020-06-15 |
Luke Kenneth Casso... | have to set up addr/st rel-go link before setting up... |
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2020-06-15 |
Luke Kenneth Casso... | add in memory setup/check but disable LDST Unit Tests... |
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2020-06-08 |
Luke Kenneth Casso... | re-add unit tests back in |
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2020-06-08 |
Luke Kenneth Casso... | more verbose debug information tracking down SO/OV... |
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2020-06-08 |
Luke Kenneth Casso... | code-morph test_core for XER bit clarity |
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2020-06-08 |
Luke Kenneth Casso... | added check which shows that OV32 in "adde." is not... |
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2020-06-07 |
Luke Kenneth Casso... | assert XER SO/OV/CA registers, check these are ok ... |
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2020-06-07 |
Luke Kenneth Casso... | add debug print statements, re-enable all tests in... |
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2020-06-07 |
Luke Kenneth Casso... | add msr to ISA in test_core.py |
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2020-06-06 |
Luke Kenneth Casso... | missing test.mem arg for ISA in test_core |
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2020-06-05 |
Luke Kenneth Casso... | comment out CR assertion for now |
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2020-06-05 |
Luke Kenneth Casso... | experimenting with CR, not quite right |
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2020-06-04 |
Luke Kenneth Casso... | testing CRs after writing: not in the right bit-order |
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2020-06-04 |
Luke Kenneth Casso... | remove unneeded code |
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2020-06-04 |
Luke Kenneth Casso... | add branch test case to core |
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2020-06-04 |
Luke Kenneth Casso... | no global variables in test suites |
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2020-06-04 |
Luke Kenneth Casso... | sigh. because POWER. CR index inversion |
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2020-06-04 |
Luke Kenneth Casso... | sigh. weirdness involving bit-inversion, inconsistency... |
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2020-06-04 |
Luke Kenneth Casso... | no global variables in test suites |
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2020-06-04 |
Luke Kenneth Casso... | add ShiftRot test case (works only because CRs are... |
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2020-06-04 |
Luke Kenneth Casso... | add both logical and ALU test core |
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2020-06-04 |
Luke Kenneth Casso... | comment clarify on core |
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2020-06-04 |
Luke Kenneth Casso... | initialise XER from simulation |
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