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PortInterfaceBase: add dcbz handling
[soc.git]
/
src
/
soc
/
simple
/
test
/
2021-05-01
Luke Kenneth Casso...
use new AllFunctionUnits.get_fu function
tree
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commitdiff
2021-05-01
Luke Kenneth Casso...
use SPRreduced to match PowerDecoder2
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
add a TestSRAM variant of LoadStore1, for being able...
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
add basic test_issuer_mmu.py
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
add option to use new mmu_cache_wb ConfigMemoryPortInte...
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
https://bugs.libre-soc.org/show_bug.cgi?id=635
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
better reporting on gpr comparisons
tree
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commitdiff
2021-04-23
Luke Kenneth Casso...
add comments on TestIssuer TestRunner
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commitdiff
2021-04-23
Luke Kenneth Casso...
comment tests back in
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commitdiff
2021-04-23
Luke Kenneth Casso...
error in setting fast regs test values
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commitdiff
2021-04-23
Luke Kenneth Casso...
import from openpower.tests
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commitdiff
2021-04-23
Luke Kenneth Casso...
use openpower.test.common
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commitdiff
2021-04-23
Luke Kenneth Casso...
move more files to openpower-isa
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commitdiff
2021-04-23
Luke Kenneth Casso...
correct migration of openpower-isa
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commitdiff
2021-04-23
Luke Kenneth Casso...
move over to from openpower imports
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commitdiff
2021-04-21
Tobias Platen
testcase: pass PRTBL to mmu
tree
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commitdiff
2021-04-03
Cesar Strauss
Allow the Simulator to handle back-to-back signaling...
tree
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commitdiff
2021-03-30
Alain D D Williams
Merge branch 'master' of git.libre-soc.org:soc
tree
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commitdiff
2021-03-30
Luke Kenneth Casso...
use port name for INT regfile to match up with test_run...
tree
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commitdiff
2021-03-30
Cesar Strauss
Memory port seems to have been renamed
tree
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commitdiff
2021-03-28
Luke Kenneth Casso...
rather invasive reduction of SPR regfile size
tree
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commitdiff
2021-03-28
Luke Kenneth Casso...
reduce number of regfile ports
tree
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commitdiff
2021-03-22
Cesar Strauss
Add traces for the new FSM and integer predicate decoding
tree
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commitdiff
2021-03-09
Cesar Strauss
Add some extra debug traces to the GTKWave document
tree
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commitdiff
2021-03-09
Cesar Strauss
Create a new signal for the Simulator to wait on
tree
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commitdiff
2021-03-08
Luke Kenneth Casso...
actually make it possible to disable svp64 on commandli...
tree
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commitdiff
2021-03-08
Luke Kenneth Casso...
add option in TestRunner to disable svp64 via commandli...
tree
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commitdiff
2021-03-03
Luke Kenneth Casso...
set SVSTATE in TestRunner using new TestIssuer.svstate_i
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commitdiff
2021-03-03
Luke Kenneth Casso...
add svstate_i to TestIssuer which mirrors pc_i
tree
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commitdiff
2021-03-02
Luke Kenneth Casso...
sort out SPR setting in MMU
tree
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commitdiff
2021-02-27
Cesar Strauss
Add traces for the new FSM
tree
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commitdiff
2021-02-24
Tobias Platen
test_runner.py: add needed imports
tree
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commitdiff
2021-02-23
Tobias Platen
deduplicate
tree
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commitdiff
2021-02-22
Luke Kenneth Casso...
whoops
tree
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commitdiff
2021-02-22
Luke Kenneth Casso...
moving PC-setting (NIA) out of execute_fsm in TestIssuer
tree
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commitdiff
2021-02-21
Cesar Strauss
Hide the register augmentation traces by default
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commitdiff
2021-02-21
Luke Kenneth Casso...
move fetch_fsm to separate function in TestIssuer
tree
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commitdiff
2021-02-21
Luke Kenneth Casso...
add JTAG enable/disable of 4k SRAMs
tree
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commitdiff
2021-02-20
Luke Kenneth Casso...
whoops set ROM to none by mistake
tree
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commitdiff
2021-02-20
Luke Kenneth Casso...
remove massive code-duplication, move simple "self...
tree
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commitdiff
2021-02-20
Tobias Platen
add rom debugger
tree
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commitdiff
2021-02-20
Tobias Platen
add mmu rom testcase
tree
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commitdiff
2021-02-17
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2021-02-17
Tobias Platen
add wishbone signals to gtkwave output
tree
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commitdiff
2021-02-17
Cesar Strauss
Add the SVSTATE traces to GTKWave to allow debugging...
tree
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commitdiff
2021-02-17
Cesar Strauss
Initialize the core SVSTATE from the corresponding...
tree
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commitdiff
2021-02-17
Cesar Strauss
Revert "Setup SVSTATE, from the test settings, at the...
tree
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commitdiff
2021-02-17
Cesar Strauss
Add traces to debug SVP64 prefix decoding issues
tree
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commitdiff
2021-02-17
Cesar Strauss
Setup SVSTATE, from the test settings, at the start
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commitdiff
2021-02-16
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2021-02-15
Tobias Platen
test case for MMU SPRs: PID and PRTBL
tree
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commitdiff
2021-02-15
Cesar Strauss
Simplify obtaining the PC from the register file
tree
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commitdiff
2021-02-15
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2021-02-14
Cesar Strauss
Show traces for the register numbers of the current...
tree
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commitdiff
2021-02-14
Luke Kenneth Casso...
add TestRunner comments
tree
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commitdiff
2021-02-13
Cesar Strauss
Check the PC value at the end of each instruction
tree
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commitdiff
2021-02-13
Luke Kenneth Casso...
add SVP64 TestIssuer separate unit test
tree
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commitdiff
2021-02-13
Luke Kenneth Casso...
split out TestRunner into separate module
tree
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commitdiff
2021-02-12
Luke Kenneth Casso...
add SVSTATE to TestCase infrastructure for use in TestI...
tree
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commitdiff
2021-02-06
Cesar Strauss
Fix whitespace
tree
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commitdiff
2021-02-06
Cesar Strauss
Extract the fetch FSM out from the main FSM
tree
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commitdiff
2021-02-04
Tobias Platen
src/soc/fu/mmu/fsm.py: add debug outputs for gtkwave
tree
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commitdiff
2021-02-01
Tobias Platen
extending the GTKWave document in test_issuer when...
tree
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commitdiff
2021-02-01
Cesar Strauss
Add GTKWave document to test_issuer
tree
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commitdiff
2021-01-18
Tobias Platen
uncomment #FIXME in unit_test
tree
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commitdiff
2021-01-16
Tobias Platen
move microwatt_mmu bool variable to pspec
tree
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commitdiff
2021-01-08
Tobias Platen
fix broken testcase for simple core
tree
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commitdiff
2020-10-16
Luke Kenneth Casso...
re-enable tests
tree
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commitdiff
2020-10-16
Luke Kenneth Casso...
manually run coresync clock for test issuer
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commitdiff
2020-10-16
Luke Kenneth Casso...
set defaults in pspec
tree
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commitdiff
2020-10-01
Luke Kenneth Casso...
create dummy PLL block, connect up to core and clock...
tree
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commitdiff
2020-09-26
Cesar Strauss
Convert a few more tests to be able to use cxxsim
tree
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commitdiff
2020-09-24
Cesar Strauss
Use nmutil simulator module to simplify choosing among...
tree
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commitdiff
2020-09-08
Luke Kenneth Casso...
add cxxsim option
tree
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commitdiff
2020-08-30
Luke Kenneth Casso...
reversal of FXM mask for one-hot selection in OP_MTCR...
tree
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commitdiff
2020-08-29
Luke Kenneth Casso...
add hack to get at XER through DMI interface
tree
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commitdiff
2020-08-27
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
tree
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commitdiff
2020-08-27
Luke Kenneth Casso...
overflow-enable does not occur on shift operations
tree
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commitdiff
2020-08-25
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
tree
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commitdiff
2020-08-25
Luke Kenneth Casso...
add CR read to DMI interface
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commitdiff
2020-08-24
Luke Kenneth Casso...
add isel CR tests to run on qemu (confirmed working)
tree
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commitdiff
2020-08-21
Luke Kenneth Casso...
get litex sim enabled with 32-bit wishbone bus
tree
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commitdiff
2020-08-16
Luke Kenneth Casso...
attempting to track down bug in litex bios memtest
tree
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commitdiff
2020-08-15
Luke Kenneth Casso...
rather big change to interaction between regfile and...
tree
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commitdiff
2020-08-14
Luke Kenneth Casso...
sync up the core decode-execute state,
tree
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commitdiff
2020-08-14
Luke Kenneth Casso...
move instruction decoder out of core
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commitdiff
2020-08-14
Luke Kenneth Casso...
sort out instruction stop/cancel when adding a new...
tree
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commitdiff
2020-08-13
Luke Kenneth Casso...
sigh. convert INT regfile to binary addressing
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commitdiff
2020-08-09
Luke Kenneth Casso...
add logical test issuer case
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commitdiff
2020-08-05
Cole Poirier
Merge branch 'master' of git.libre-soc.org:soc
tree
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commitdiff
2020-08-05
Luke Kenneth Casso...
add div test cases into test_issuer.py
tree
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commitdiff
2020-08-03
Luke Kenneth Casso...
add quick demo/test of reading DMI reg 9
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commitdiff
2020-08-03
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-08-03
Luke Kenneth Casso...
change over to DMI debug start/stop interface
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commitdiff
2020-07-29
Jacob Lifshay
add __init__.py to all source directories
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commitdiff
2020-07-29
Jacob Lifshay
format some tests
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commitdiff
2020-07-26
Luke Kenneth Casso...
add nop test cases
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commitdiff
2020-07-26
Luke Kenneth Casso...
activate some of new accumulator-based tests in test_issuer
tree
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commitdiff
2020-07-23
Luke Kenneth Casso...
support 32-bit mem width setting
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commitdiff
2020-07-22
Jacob Lifshay
Merge remote-tracking branch 'origin/master'
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commitdiff
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