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add option to run ISACaller Sim (or not)
[soc.git]
/
src
/
soc
/
simple
/
test
/
2021-09-23
Luke Kenneth Casso...
add option to run ISACaller Sim (or not)
tree
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commitdiff
2021-09-23
Luke Kenneth Casso...
add a new run_hdl parameter to TestRunner
tree
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commitdiff
2021-09-22
Luke Kenneth Casso...
completely borked python segfault, workaround to copy...
tree
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commitdiff
2021-09-22
Luke Kenneth Casso...
add test of expected results against last sim state
tree
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commitdiff
2021-09-22
Luke Kenneth Casso...
whoops broken run_sim_state function
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commitdiff
2021-09-22
Luke Kenneth Casso...
split out HDL from Simulator into separate functions
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commitdiff
2021-09-22
Luke Kenneth Casso...
split out HDL test from Simulator test,
tree
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commitdiff
2021-09-22
Luke Kenneth Casso...
alter setup_tst_memory to take a test.mem rather than...
tree
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commitdiff
2021-09-22
Luke Kenneth Casso...
whoops forgot to do with self.subTest()
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commitdiff
2021-09-21
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2021-09-21
klehman
changed test_runner to use state mem compare
tree
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commitdiff
2021-09-21
klehman
changed over to use state mem compare
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commitdiff
2021-09-21
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2021-09-21
Luke Kenneth Casso...
convert HDLState.get_mem() to a dictionary of memory...
tree
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commitdiff
2021-09-20
Luke Kenneth Casso...
use get_l0_mem in HDLState to get memory data
tree
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commitdiff
2021-09-18
Luke Kenneth Casso...
allow individual unit tests to be named in test_issuer.py
tree
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commitdiff
2021-09-18
Luke Kenneth Casso...
always store full memory state (including zeros)
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commitdiff
2021-09-18
klehman
added get_mem
tree
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commitdiff
2021-09-17
Luke Kenneth Casso...
update comments
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commitdiff
2021-09-16
Luke Kenneth Casso...
moving teststate_check_regs written by klehman into...
tree
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commitdiff
2021-09-15
isengaara
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2021-09-14
Luke Kenneth Casso...
convert to using TestState and State after moving to...
tree
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commitdiff
2021-09-14
klehman
factory add and intro doc string
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commitdiff
2021-09-12
Luke Kenneth Casso...
use log instead of print
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commitdiff
2021-09-12
Luke Kenneth Casso...
code comments
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commitdiff
2021-09-12
Luke Kenneth Casso...
create new function teststate_check_regs which is calle...
tree
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commitdiff
2021-09-12
klehman
changes to utilize full teststate class
tree
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commitdiff
2021-09-12
klehman
added compare function
tree
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commitdiff
2021-09-12
klehman
added factory function for test class creation
tree
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commitdiff
2021-09-10
klehman
implement base class in state class
tree
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commitdiff
2021-09-10
klehman
changes made to utilize teststate class
tree
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commitdiff
2021-09-09
klehman
made sim into generators and some uniformity changes
tree
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commitdiff
2021-09-09
klehman
finished remaining hdl items
tree
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commitdiff
2021-09-09
klehman
HDL int reg added
tree
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commitdiff
2021-09-09
klehman
more sim class registers add
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commitdiff
2021-09-08
Cesar Strauss
Monitor exceptions, re-decoding the instruction in...
tree
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commitdiff
2021-09-08
klehman
initial commit of sim state class
tree
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commitdiff
2021-09-08
Cesar Strauss
Monitor the exception input to PowerDecoder2
tree
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commitdiff
2021-09-07
Luke Kenneth Casso...
fun fixing of get_core_hdl_regs, "yield from"
tree
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commitdiff
2021-09-07
Luke Kenneth Casso...
move functions to above where they are called
tree
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commitdiff
2021-09-07
klehman
breakout of register collection and compare
tree
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commitdiff
2021-09-07
Cesar Strauss
Fix typo.
tree
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commitdiff
2021-09-07
Luke Kenneth Casso...
add TODO code-comments
tree
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commitdiff
2021-09-07
Luke Kenneth Casso...
whitespace, add bug ref number to test API
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commitdiff
2021-08-29
Luke Kenneth Casso...
unnecessary signal rename ivalid_i to ii_valid (reverting)
tree
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commitdiff
2021-08-24
Luke Kenneth Casso...
replace data_o with o_data and data_i with i_data as...
tree
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commitdiff
2021-08-24
Luke Kenneth Casso...
big rename, global/search/replace of ready_o with o_rea...
tree
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commitdiff
2021-08-17
Cesar Strauss
Enable LD/ST exception test case
tree
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commitdiff
2021-08-16
Cesar Strauss
Adjust PortInterface traces according to MMU option
tree
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commitdiff
2021-08-16
Tobias Platen
add WIP DCBZTestCase
tree
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commitdiff
2021-08-01
Jonathan Neuschäfer
import setup_i_memory from soc.simple.test.test_runner
tree
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commitdiff
2021-08-01
Jonathan Neuschäfer
soc.simple.test: Rename setup_test_memory to avoid...
tree
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commitdiff
2021-07-24
Tobias Platen
add test_issuer_dcache.py
tree
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commitdiff
2021-07-15
Luke Kenneth Casso...
update TestRunner, SVSTATE is now a class that inherits...
tree
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commitdiff
2021-07-14
Luke Kenneth Casso...
update SVSTATE to 64 bit length (fortunately very easy)
tree
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commitdiff
2021-07-12
Luke Kenneth Casso...
use standard create_pdecode in TestRunner
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commitdiff
2021-07-11
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2021-07-10
Cesar Strauss
Show some usage of PortInterface in action
tree
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commitdiff
2021-05-22
Cesar Strauss
Move the reset code outside of the sub-test
tree
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commitdiff
2021-05-12
Luke Kenneth Casso...
bit of a hack to get test_mmu_dcache_pi.py operational.
tree
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commitdiff
2021-05-10
Luke Kenneth Casso...
add block for MMU activation to LoadStore1
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commitdiff
2021-05-09
Luke Kenneth Casso...
add comments in LoadStore1
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commitdiff
2021-05-09
Luke Kenneth Casso...
run LD/ST Exception test case for MMU
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commitdiff
2021-05-07
Luke Kenneth Casso...
how we managed to get this far without noticing that...
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commitdiff
2021-05-06
Luke Kenneth Casso...
whoops disabled tests agaaaaain
tree
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commitdiff
2021-05-06
Luke Kenneth Casso...
add in predicate mask bit detection when zeroing is...
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commitdiff
2021-05-06
Luke Kenneth Casso...
moved exts* SVP64 unit tests to a different location
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commitdiff
2021-05-04
Luke Kenneth Casso...
whoops disabled some test_issuer group tests
tree
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commitdiff
2021-05-04
Luke Kenneth Casso...
code-comments for LDSTCompUnit
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commitdiff
2021-05-01
Luke Kenneth Casso...
send a DMI RESET at the end of the test.
tree
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commitdiff
2021-05-01
Luke Kenneth Casso...
store data in microwatt dcache goes in one cycle AFTER...
tree
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commitdiff
2021-05-01
Luke Kenneth Casso...
add LD/ST cases to MMU, which should all still work
tree
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commitdiff
2021-05-01
Luke Kenneth Casso...
add MMUTestCaseROM
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commitdiff
2021-05-01
Luke Kenneth Casso...
use new AllFunctionUnits.get_fu function
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commitdiff
2021-05-01
Luke Kenneth Casso...
use SPRreduced to match PowerDecoder2
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commitdiff
2021-04-30
Luke Kenneth Casso...
add a TestSRAM variant of LoadStore1, for being able...
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
add basic test_issuer_mmu.py
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
add option to use new mmu_cache_wb ConfigMemoryPortInte...
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
https://bugs.libre-soc.org/show_bug.cgi?id=635
tree
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commitdiff
2021-04-30
Luke Kenneth Casso...
better reporting on gpr comparisons
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commitdiff
2021-04-23
Luke Kenneth Casso...
add comments on TestIssuer TestRunner
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commitdiff
2021-04-23
Luke Kenneth Casso...
comment tests back in
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commitdiff
2021-04-23
Luke Kenneth Casso...
error in setting fast regs test values
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commitdiff
2021-04-23
Luke Kenneth Casso...
import from openpower.tests
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commitdiff
2021-04-23
Luke Kenneth Casso...
use openpower.test.common
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commitdiff
2021-04-23
Luke Kenneth Casso...
move more files to openpower-isa
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commitdiff
2021-04-23
Luke Kenneth Casso...
correct migration of openpower-isa
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commitdiff
2021-04-23
Luke Kenneth Casso...
move over to from openpower imports
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commitdiff
2021-04-21
Tobias Platen
testcase: pass PRTBL to mmu
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commitdiff
2021-04-03
Cesar Strauss
Allow the Simulator to handle back-to-back signaling...
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commitdiff
2021-03-30
Alain D D Williams
Merge branch 'master' of git.libre-soc.org:soc
tree
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commitdiff
2021-03-30
Luke Kenneth Casso...
use port name for INT regfile to match up with test_run...
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commitdiff
2021-03-30
Cesar Strauss
Memory port seems to have been renamed
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commitdiff
2021-03-28
Luke Kenneth Casso...
rather invasive reduction of SPR regfile size
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commitdiff
2021-03-28
Luke Kenneth Casso...
reduce number of regfile ports
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commitdiff
2021-03-22
Cesar Strauss
Add traces for the new FSM and integer predicate decoding
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commitdiff
2021-03-09
Cesar Strauss
Add some extra debug traces to the GTKWave document
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commitdiff
2021-03-09
Cesar Strauss
Create a new signal for the Simulator to wait on
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commitdiff
2021-03-08
Luke Kenneth Casso...
actually make it possible to disable svp64 on commandli...
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commitdiff
2021-03-08
Luke Kenneth Casso...
add option in TestRunner to disable svp64 via commandli...
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commitdiff
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