2021-10-01 |
Luke Kenneth Casso... | move TestRunner to openpower-isa now that it is part... |
tree | commitdiff |
2021-09-26 |
klehman | add a state list for method calling |
tree | commitdiff |
2021-09-25 |
Luke Kenneth Casso... | found accidental commenting-out of memory setup in... |
tree | commitdiff |
2021-09-25 |
Luke Kenneth Casso... | move debug printout to see whats going on for ldst |
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2021-09-25 |
Luke Kenneth Casso... | comments |
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2021-09-25 |
Luke Kenneth Casso... | Revert "move coresync clock synchronisation into HDLRunner" |
tree | commitdiff |
2021-09-25 |
Luke Kenneth Casso... | call StateRunner constructor, to add to StateRunner... |
tree | commitdiff |
2021-09-25 |
Luke Kenneth Casso... | more TODO comments |
tree | commitdiff |
2021-09-25 |
Luke Kenneth Casso... | move coresync clock synchronisation into HDLRunner |
tree | commitdiff |
2021-09-25 |
Luke Kenneth Casso... | whoops missed one function which should be a yield... |
tree | commitdiff |
2021-09-25 |
Luke Kenneth Casso... | use yield from on StateRunners |
tree | commitdiff |
2021-09-25 |
Luke Kenneth Casso... | add comments, remove unneeded code |
tree | commitdiff |
2021-09-25 |
Luke Kenneth Casso... | move pc_i and svstate_i to HDLRunner |
tree | commitdiff |
2021-09-25 |
klehman | add end_test, minor cleanup, added hdlrun.cleanup(... |
tree | commitdiff |
2021-09-25 |
klehman | moved pc_i and sv_state to constructor, remove hdl_stat... |
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2021-09-25 |
klehman | change over run_hdl_state to TestRunner class |
tree | commitdiff |
2021-09-25 |
Luke Kenneth Casso... | add dummy call to simrun and end_test() |
tree | commitdiff |
2021-09-25 |
Luke Kenneth Casso... | code-comments and dummy functions |
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2021-09-25 |
Luke Kenneth Casso... | move contents of run_sim_state into SimRunner run_test... |
tree | commitdiff |
2021-09-25 |
Luke Kenneth Casso... | add a SimRunner prepare_for_test and run_test function |
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2021-09-25 |
klehman | start of HDLRunner |
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2021-09-24 |
Luke Kenneth Casso... | create initial SimRunner |
tree | commitdiff |
2021-09-24 |
Luke Kenneth Casso... | add shiftrot2 tests to test_issuer.py |
tree | commitdiff |
2021-09-23 |
Luke Kenneth Casso... | move pc_i and svstate_i inside if self.run_hdl |
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2021-09-23 |
Luke Kenneth Casso... | more comments |
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2021-09-23 |
Luke Kenneth Casso... | add in a stack of comments for identifying match-points... |
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2021-09-23 |
Luke Kenneth Casso... | add option to run ISACaller Sim (or not) |
tree | commitdiff |
2021-09-23 |
Luke Kenneth Casso... | add a new run_hdl parameter to TestRunner |
tree | commitdiff |
2021-09-22 |
Luke Kenneth Casso... | completely borked python segfault, workaround to copy... |
tree | commitdiff |
2021-09-22 |
Luke Kenneth Casso... | add test of expected results against last sim state |
tree | commitdiff |
2021-09-22 |
Luke Kenneth Casso... | whoops broken run_sim_state function |
tree | commitdiff |
2021-09-22 |
Luke Kenneth Casso... | split out HDL from Simulator into separate functions |
tree | commitdiff |
2021-09-22 |
Luke Kenneth Casso... | split out HDL test from Simulator test, |
tree | commitdiff |
2021-09-22 |
Luke Kenneth Casso... | alter setup_tst_memory to take a test.mem rather than... |
tree | commitdiff |
2021-09-22 |
Luke Kenneth Casso... | whoops forgot to do with self.subTest() |
tree | commitdiff |
2021-09-21 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-09-21 |
klehman | changed test_runner to use state mem compare |
tree | commitdiff |
2021-09-21 |
klehman | changed over to use state mem compare |
tree | commitdiff |
2021-09-21 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-09-21 |
Luke Kenneth Casso... | convert HDLState.get_mem() to a dictionary of memory... |
tree | commitdiff |
2021-09-20 |
Luke Kenneth Casso... | use get_l0_mem in HDLState to get memory data |
tree | commitdiff |
2021-09-18 |
Luke Kenneth Casso... | allow individual unit tests to be named in test_issuer.py |
tree | commitdiff |
2021-09-18 |
Luke Kenneth Casso... | always store full memory state (including zeros) |
tree | commitdiff |
2021-09-18 |
klehman | added get_mem |
tree | commitdiff |
2021-09-17 |
Luke Kenneth Casso... | update comments |
tree | commitdiff |
2021-09-16 |
Luke Kenneth Casso... | moving teststate_check_regs written by klehman into... |
tree | commitdiff |
2021-09-15 |
isengaara | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-09-14 |
Luke Kenneth Casso... | convert to using TestState and State after moving to... |
tree | commitdiff |
2021-09-14 |
klehman | factory add and intro doc string |
tree | commitdiff |
2021-09-12 |
Luke Kenneth Casso... | use log instead of print |
tree | commitdiff |
2021-09-12 |
Luke Kenneth Casso... | code comments |
tree | commitdiff |
2021-09-12 |
Luke Kenneth Casso... | create new function teststate_check_regs which is calle... |
tree | commitdiff |
2021-09-12 |
klehman | changes to utilize full teststate class |
tree | commitdiff |
2021-09-12 |
klehman | added compare function |
tree | commitdiff |
2021-09-12 |
klehman | added factory function for test class creation |
tree | commitdiff |
2021-09-10 |
klehman | implement base class in state class |
tree | commitdiff |
2021-09-10 |
klehman | changes made to utilize teststate class |
tree | commitdiff |
2021-09-10 |
Luke Kenneth Casso... | update explanatory comments on LD/ST exception handling |
tree | commitdiff |
2021-09-09 |
klehman | made sim into generators and some uniformity changes |
tree | commitdiff |
2021-09-09 |
klehman | finished remaining hdl items |
tree | commitdiff |
2021-09-09 |
klehman | HDL int reg added |
tree | commitdiff |
2021-09-09 |
klehman | more sim class registers add |
tree | commitdiff |
2021-09-08 |
Cesar Strauss | Monitor exceptions, re-decoding the instruction in... |
tree | commitdiff |
2021-09-08 |
klehman | initial commit of sim state class |
tree | commitdiff |
2021-09-08 |
Cesar Strauss | Monitor the exception input to PowerDecoder2 |
tree | commitdiff |
2021-09-07 |
Luke Kenneth Casso... | fun fixing of get_core_hdl_regs, "yield from" |
tree | commitdiff |
2021-09-07 |
Luke Kenneth Casso... | move functions to above where they are called |
tree | commitdiff |
2021-09-07 |
klehman | breakout of register collection and compare |
tree | commitdiff |
2021-09-07 |
Cesar Strauss | Fix typo. |
tree | commitdiff |
2021-09-07 |
Luke Kenneth Casso... | add TODO code-comments |
tree | commitdiff |
2021-09-07 |
Luke Kenneth Casso... | whitespace, add bug ref number to test API |
tree | commitdiff |
2021-08-29 |
Luke Kenneth Casso... | unnecessary signal rename ivalid_i to ii_valid (reverting) |
tree | commitdiff |
2021-08-24 |
Luke Kenneth Casso... | replace data_o with o_data and data_i with i_data as... |
tree | commitdiff |
2021-08-24 |
Luke Kenneth Casso... | big rename, global/search/replace of ready_o with o_rea... |
tree | commitdiff |
2021-08-17 |
Cesar Strauss | Enable LD/ST exception test case |
tree | commitdiff |
2021-08-16 |
Cesar Strauss | Adjust PortInterface traces according to MMU option |
tree | commitdiff |
2021-08-16 |
Tobias Platen | add WIP DCBZTestCase |
tree | commitdiff |
2021-08-01 |
Jonathan Neuschäfer | import setup_i_memory from soc.simple.test.test_runner |
tree | commitdiff |
2021-08-01 |
Jonathan Neuschäfer | soc.simple.test: Rename setup_test_memory to avoid... |
tree | commitdiff |
2021-07-24 |
Tobias Platen | add test_issuer_dcache.py |
tree | commitdiff |
2021-07-15 |
Luke Kenneth Casso... | update TestRunner, SVSTATE is now a class that inherits... |
tree | commitdiff |
2021-07-14 |
Luke Kenneth Casso... | update SVSTATE to 64 bit length (fortunately very easy) |
tree | commitdiff |
2021-07-12 |
Luke Kenneth Casso... | use standard create_pdecode in TestRunner |
tree | commitdiff |
2021-07-12 |
Luke Kenneth Casso... | use default decoder, do not pass one in. |
tree | commitdiff |
2021-07-11 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-07-10 |
Cesar Strauss | Show some usage of PortInterface in action |
tree | commitdiff |
2021-06-24 |
Luke Kenneth Casso... | propagate new use_svp64_ldst_dec mode through TestCore... |
tree | commitdiff |
2021-06-24 |
Luke Kenneth Casso... | add an explicit PowerDecoder.is_svp64_mode flag to... |
tree | commitdiff |
2021-06-09 |
Luke Kenneth Casso... | disconnect pll clock, connected in peripheral interconnect |
tree | commitdiff |
2021-06-09 |
Luke Kenneth Casso... | add in/out of ref_clk and pllclk_clk when PLL enabled |
tree | commitdiff |
2021-06-03 |
Luke Kenneth Casso... | comment out domains that have already been created |
tree | commitdiff |
2021-06-03 |
Luke Kenneth Casso... | no, do not assign clock to clock! |
tree | commitdiff |
2021-06-03 |
Luke Kenneth Casso... | sort out PLL domains but bypass PLL due to lack of... |
tree | commitdiff |
2021-06-03 |
Luke Kenneth Casso... | use DomainRenamer on all sub-components of TestIssuer |
tree | commitdiff |
2021-06-03 |
Luke Kenneth Casso... | make core_rst a member of TestIssuerInternal |
tree | commitdiff |
2021-05-27 |
Luke Kenneth Casso... | adjust PLL connections looking for coriolis2 issue |
tree | commitdiff |
2021-05-26 |
Luke Kenneth Casso... | arse. PLL test_issuer clk_sel_i accidentally only 1... |
tree | commitdiff |
2021-05-26 |
Luke Kenneth Casso... | remove err feature from sram4k wb |
tree | commitdiff |
2021-05-26 |
Luke Kenneth Casso... | rename PLL signals |
tree | commitdiff |
2021-05-24 |
Luke Kenneth Casso... | match up PLL names |
tree | commitdiff |
next |