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add regression test for div overflow case
[soc.git]
/
src
/
soc
/
2020-07-09
Luke Kenneth Casso...
add regression test for div overflow case
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2020-07-09
Luke Kenneth Casso...
slightly different so handling in common output stage
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2020-07-09
Luke Kenneth Casso...
also set so only if OE requires it
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2020-07-09
Luke Kenneth Casso...
debug information related to 32/64 bit mode
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2020-07-09
Luke Kenneth Casso...
bug #424 - 32/64 bit is a *global* flag not a per-op one
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2020-07-09
Luke Kenneth Casso...
test top bit 31 in 32-bit mode for CR0 creation
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2020-07-09
Luke Kenneth Casso...
ha ha very funny. pipelines being pipelines, you have...
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2020-07-09
Luke Kenneth Casso...
whoops test gets copied 4 times on the If.
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2020-07-09
Luke Kenneth Casso...
ALU output stage, change logic slightly
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2020-07-09
Luke Kenneth Casso...
set xer_ov.ok = 1
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2020-07-09
Luke Kenneth Casso...
remove unneeded xer.ca in MulOutputData
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2020-07-09
Luke Kenneth Casso...
something weird going on with div. interaction between...
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2020-07-09
Luke Kenneth Casso...
simplify setting of mul overflow into xer_ov
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2020-07-09
Luke Kenneth Casso...
clarifying comments on setting xer_ov/so
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2020-07-09
Luke Kenneth Casso...
DIV overflow needs to be copied into both bits of XER.ov
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2020-07-09
Luke Kenneth Casso...
add debug output of DIV results
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2020-07-09
Luke Kenneth Casso...
check result first then CR second
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2020-07-09
Luke Kenneth Casso...
munge alu_fsm Shifter into looking like CompALU API...
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2020-07-09
Luke Kenneth Casso...
resolving issues with div tests (turned out to be nmuti...
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2020-07-09
Luke Kenneth Casso...
remove xer_ca from DIV pipeline (took a bit of messing...
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2020-07-09
Cesar Strauss
Define ports for a simple sequential Shifter
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2020-07-09
Luke Kenneth Casso...
irony comment on how one line creates a massive array...
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2020-07-09
Luke Kenneth Casso...
add new stages etc. to get multiply working without...
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2020-07-09
Luke Kenneth Casso...
create new DivMulOutputData which does not have CA...
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2020-07-09
Luke Kenneth Casso...
make carry output handling optional in common output...
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2020-07-09
Luke Kenneth Casso...
identifying locations where big/little endian is in...
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2020-07-08
Luke Kenneth Casso...
resolving bigendian/littleendian modes in qemu sim
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2020-07-08
Luke Kenneth Casso...
resolving old and new behaviour for lookup of SPRs
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2020-07-08
Luke Kenneth Casso...
resolving old and new behaviour for lookup of SPRs
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2020-07-08
Luke Kenneth Casso...
adding in ALU test back in, debugging SPR setup
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2020-07-08
Luke Kenneth Casso...
sorting out setting of XER
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2020-07-08
Luke Kenneth Casso...
add spr to fast reg converter
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2020-07-08
Luke Kenneth Casso...
got test_issuer operational on one unit test
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2020-07-08
Luke Kenneth Casso...
switch assembler to little-endian
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2020-07-08
Luke Kenneth Casso...
stashing current state of investigation whilst looking...
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2020-07-08
Luke Kenneth Casso...
add test trap simulator unit test
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2020-07-08
Luke Kenneth Casso...
allow qemu to stop at specified end point
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2020-07-08
Luke Kenneth Casso...
add mtspr and bcctrl instructions to helloworld test
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2020-07-08
Luke Kenneth Casso...
add option to qemu to break at known alternate address
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2020-07-08
Luke Kenneth Casso...
add to/from spr test (mtspr, mfspr)
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2020-07-08
Luke Kenneth Casso...
add code-fragment from microwatt helloworld
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2020-07-08
Luke Kenneth Casso...
add a simple addis test (regression)
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2020-07-08
Luke Kenneth Casso...
copy binary loaded from disk into data memory as well
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2020-07-08
Cesar Strauss
Start the FSM-based ALU example.
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commitdiff
2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-07
Luke Kenneth Casso...
add hello world binary test
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2020-07-07
Luke Kenneth Casso...
whoops error in test of dynamic parameter
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2020-07-07
Luke Kenneth Casso...
sort-of got binary execution test working
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2020-07-07
Luke Kenneth Casso...
code-shuffle on testing to prepare loading large files...
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2020-07-07
Cesar Strauss
Clear input data along with valid_i
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2020-07-07
Luke Kenneth Casso...
ordering of tests for OP_ATTN needed shuffling. seems...
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2020-07-07
Luke Kenneth Casso...
whoops got Function.NONE test wrong in PowerDecode2
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2020-07-07
Luke Kenneth Casso...
remove unneeded record field from logical_input_record
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2020-07-07
Luke Kenneth Casso...
debugging termination (OP_ATTN)
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2020-07-07
Luke Kenneth Casso...
update opcode map for OP_ATTN
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2020-07-07
Luke Kenneth Casso...
add halted condition in ISACaller, when attn instructio...
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2020-07-07
Luke Kenneth Casso...
debugging termination / OP_ATTN
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2020-07-07
Luke Kenneth Casso...
add ATTN unit test
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2020-07-07
Luke Kenneth Casso...
add core start/stop capability, and OP_ATTN support
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2020-07-07
Luke Kenneth Casso...
add in SPR test cases into test_issuer.py
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2020-07-06
Luke Kenneth Casso...
use ComMULOpSubset in mul pipeline
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2020-07-06
Luke Kenneth Casso...
remove alu unneeded op record data
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2020-07-06
Luke Kenneth Casso...
remove alu unneeded op record data
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2020-07-06
Luke Kenneth Casso...
remove alu unneeded op record data
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2020-07-06
Luke Kenneth Casso...
add mul unit to test_issuer
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2020-07-06
Luke Kenneth Casso...
add mul compunit
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2020-07-06
Luke Kenneth Casso...
whoops forgot that the mul pipeline is actually a pipel...
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2020-07-06
Luke Kenneth Casso...
do abs slightly differently in SelectableInt
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2020-07-06
Luke Kenneth Casso...
continue mul unit test debugging
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2020-07-06
Luke Kenneth Casso...
add MULS (signed) version of multiply
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2020-07-06
Luke Kenneth Casso...
improve debug for test_sim.py
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2020-07-06
Luke Kenneth Casso...
add mullw test to qemu sim
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2020-07-06
Luke Kenneth Casso...
fix SelectableInt abs
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2020-07-06
Luke Kenneth Casso...
add first simulator mul test
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2020-07-06
Luke Kenneth Casso...
investigating mul pipeline
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2020-07-06
Luke Kenneth Casso...
SelectableInt: make __mul__ return enough space to...
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2020-07-06
Luke Kenneth Casso...
first cut at mul test pipeline
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2020-07-06
Luke Kenneth Casso...
add first cut at fu mul pipeline
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2020-07-06
Luke Kenneth Casso...
adding mtspr tests
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2020-07-06
Luke Kenneth Casso...
adding OP_MTMSR test
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2020-07-06
Luke Kenneth Casso...
add mtmsr internal op
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2020-07-06
Luke Kenneth Casso...
add mtmsr internal op
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2020-07-06
Luke Kenneth Casso...
sort out initialisation of TstL0CacheBuffer in ldst...
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2020-07-06
Cesar Strauss
Assert n.ready_i at the beginning of the cycle
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2020-07-06
Cesar Strauss
Remove wait state to demonstrate zero-delay reception.
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2020-07-06
Cesar Strauss
Simplify waiting loops
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2020-07-06
Cesar Strauss
Finally add some well needed comments
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commitdiff
2020-07-06
Cesar Strauss
Simplify waiting loops
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2020-07-06
Cesar Strauss
Add some wait states in each process
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commitdiff
2020-07-06
Cesar Strauss
Negate inputs after use
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2020-07-06
Cesar Strauss
Add other tests
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2020-07-06
Cesar Strauss
Implement receiver
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2020-07-06
Cesar Strauss
Implement sender.
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2020-07-06
Cesar Strauss
Begin a new parallel test
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2020-07-05
Luke Kenneth Casso...
add mtmsr tests (fail)
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2020-07-05
Luke Kenneth Casso...
check trap compunit output properly
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2020-07-05
Luke Kenneth Casso...
check msr in trap test, fix OP_RFID
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2020-07-05
Luke Kenneth Casso...
add an illegal instruction trap test
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2020-07-05
Luke Kenneth Casso...
set up a trap function for microcode override
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2020-07-05
Luke Kenneth Casso...
big reorg on PowerDecoder2, actually Decode2Execute1Type
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