2020-05-10 |
Michael Nolan | Reduce BMC depth on proof_main_stage.py |
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2020-05-10 |
Luke Kenneth Casso... | use temporary python vars rather than copy signals... |
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2020-05-09 |
Michael Nolan | Add shift left and shift right to main stage proof |
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2020-05-09 |
Luke Kenneth Casso... | sigh ton of syntax errors |
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2020-05-09 |
Luke Kenneth Casso... | bit of reorg, trick on add - put carry in into the LSB |
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2020-05-09 |
Luke Kenneth Casso... | comment output stage |
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2020-05-09 |
Luke Kenneth Casso... | comment maskgen |
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2020-05-09 |
Michael Nolan | Handle algebraic shifts too |
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2020-05-09 |
Michael Nolan | Implement logical shift right |
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2020-05-09 |
Michael Nolan | Add support for sld |
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2020-05-09 |
Michael Nolan | Change shift left to be implemented with rotate and... |
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2020-05-09 |
Michael Nolan | Add mask generator for shift class instructions |
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2020-05-09 |
Michael Nolan | Add shift left opcode to main_stage |
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2020-05-09 |
Michael Nolan | Fix broken mask when x == y |
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2020-05-09 |
Michael Nolan | Add right shift test to test_caller.py |
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2020-05-09 |
Michael Nolan | Add shift test to test_caller, fix fixedshift being... |
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2020-05-09 |
Michael Nolan | Fix helpers.py not playing nicely with selectableInts |
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2020-05-09 |
Michael Nolan | Add reversed add and subtract, as well as lshift and... |
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2020-05-09 |
Luke Kenneth Casso... | comment where ALUIntermediateData to go |
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2020-05-09 |
Luke Kenneth Casso... | TODO on AluIntermediateData |
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2020-05-09 |
Luke Kenneth Casso... | missing sticky-overflow pass-through from middle stage |
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2020-05-09 |
Luke Kenneth Casso... | pass through sticky-overflow |
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2020-05-09 |
Luke Kenneth Casso... | remove unneeded class |
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2020-05-09 |
Luke Kenneth Casso... | clarifying comments |
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2020-05-09 |
Michael Nolan | Minor cleanup |
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2020-05-09 |
Luke Kenneth Casso... | preliminary test for LD/ST "update" mode working |
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2020-05-09 |
Luke Kenneth Casso... | document PowerOp |
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2020-05-08 |
Luke Kenneth Casso... | add comments |
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2020-05-08 |
Luke Kenneth Casso... | add ALUFirstInputData |
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2020-05-08 |
Luke Kenneth Casso... | send address to memory only for one cycle and acknowled... |
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2020-05-08 |
Luke Kenneth Casso... | experimenting |
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2020-05-08 |
Luke Kenneth Casso... | working indexed version of LD/ST CompUnit |
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2020-05-08 |
Luke Kenneth Casso... | hmmm i think LD/ST Comp Unit might actually be working... |
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2020-05-08 |
Michael Nolan | Oops, forgot pipeline.py |
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2020-05-08 |
Michael Nolan | Add tests for immediates, add subf to tests |
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2020-05-08 |
Michael Nolan | Add comments about the purpose of each alu stage |
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2020-05-08 |
Michael Nolan | Add test for alu against simulator |
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2020-05-08 |
Michael Nolan | Add assertions for output stage cr0 |
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2020-05-08 |
Michael Nolan | Add output stage |
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2020-05-08 |
Michael Nolan | Add and or and xor to main_stage |
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2020-05-08 |
Michael Nolan | Add carry in and out |
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2020-05-08 |
Michael Nolan | Have input_stage set the b operand to imm_data if it... |
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2020-05-08 |
Michael Nolan | Add extra bits (carry, overflow, etc) to input and... |
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2020-05-08 |
Michael Nolan | Begin adding main ALU stage |
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2020-05-08 |
Michael Nolan | Convert alu to use the op in ctx |
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2020-05-08 |
Michael Nolan | Add FPPipeContext to alu pipe_data |
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2020-05-08 |
Luke Kenneth Casso... | almost got LD/ST CompUnit working |
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2020-05-08 |
Luke Kenneth Casso... | prototype LD/ST L0 cache/buffer was bouncing address... |
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2020-05-08 |
Michael Nolan | Add handling of A inversion and B input |
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2020-05-08 |
Michael Nolan | Begin adding input stage of alu |
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2020-05-08 |
Michael Nolan | Add pipe data for ALU pipeline |
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2020-05-08 |
Michael Nolan | Update gitignore in isa dir |
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2020-05-08 |
Michael Nolan | Separate out ALU Input record from alu_hier.py |
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2020-05-07 |
Michael Nolan | Add test_branch_loop_ctr |
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2020-05-07 |
Michael Nolan | Add tests for conditional branches |
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2020-05-07 |
Luke Kenneth Casso... | move unused simulator code out the way |
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2020-05-07 |
Luke Kenneth Casso... | testing LD without ST |
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2020-05-07 |
Michael Nolan | Ooops, forgot comparefixed.patch |
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2020-05-07 |
Michael Nolan | Get test_cmp working |
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2020-05-07 |
Michael Nolan | Fix test_mtcrf. Test has been verified against qemu |
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2020-05-07 |
Michael Nolan | Make FieldSelectableInt accept slices for set and get |
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2020-05-07 |
Michael Nolan | Add handling of add with comparison |
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2020-05-07 |
Michael Nolan | Fix bug with comparisons in selectable_int.py |
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2020-05-07 |
Michael Nolan | Add test_mfcr |
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2020-05-07 |
Luke Kenneth Casso... | continuing debugging of LD/ST CompUnit FSM and unit... |
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2020-05-07 |
Luke Kenneth Casso... | partially-debugged ld/st comp unit using new PortInterface |
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2020-05-06 |
Michael Nolan | Re-enable test_mtcrf |
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2020-05-06 |
Michael Nolan | Add length helper for getting length of a selectable int |
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2020-05-06 |
Michael Nolan | Add helper functions to replace direct comparison in... |
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2020-05-06 |
Luke Kenneth Casso... | no syntax errors in LDSTCompUnit multi version |
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2020-05-06 |
Luke Kenneth Casso... | almost complete LD/ST CompUnit, nearing testing |
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2020-05-06 |
Michael Nolan | Look up spr length from spr table |
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2020-05-06 |
Michael Nolan | Add dict of spr properties to power_enums |
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2020-05-06 |
Michael Nolan | Implement bctr and mtspr |
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2020-05-06 |
Michael Nolan | Properly implement LR and CTR |
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2020-05-06 |
Michael Nolan | Add ability to patch generated isa files |
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2020-05-06 |
Michael Nolan | Sorta kinda working bl and blr - need to properly imple... |
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2020-05-06 |
Luke Kenneth Casso... | remove unneeded minerva code |
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2020-05-06 |
Luke Kenneth Casso... | mention need for DualPortSplitter class |
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2020-05-06 |
Luke Kenneth Casso... | more connecting signals for LDSTCompUnit according... |
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2020-05-05 |
Michael Nolan | Add rudimentary branch capability |
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2020-05-05 |
Michael Nolan | Fix broken test_decoder_gas |
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2020-05-05 |
Luke Kenneth Casso... | begin connecting up signals for LDSTCompUnit |
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2020-05-05 |
Yehowshua Immanuel | Merge branch 'master' of git.libre-riscv.org:soc |
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2020-05-05 |
Yehowshua Immanuel | Git rid of named tuple imported twice |
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2020-05-05 |
Luke Kenneth Casso... | new version of LDSTCompUnit |
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2020-05-04 |
Luke Kenneth Casso... | comments |
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2020-05-04 |
Luke Kenneth Casso... | take out wait for busy in L0BufferCache tests |
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2020-05-04 |
Luke Kenneth Casso... | whitespace cleanup |
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2020-05-04 |
Luke Kenneth Casso... | bit of a mess, but functional. unit test passes on... |
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2020-05-04 |
Luke Kenneth Casso... | hmmm trying to get st to acknowledge properly |
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2020-05-04 |
Luke Kenneth Casso... | add links to bugreport and to memory/cache wiki page |
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2020-05-04 |
Luke Kenneth Casso... | L0 cache/buffer first unit test, working except for... |
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2020-05-04 |
Yehowshua Immanuel | Remove request since no longer https fetches from wiki |
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2020-05-04 |
Tobias Platen | update cr0 when rc is set |
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2020-05-04 |
Luke Kenneth Casso... | first cut at "basic" L0 Cache/Buffer (untested), only... |
tree | commitdiff |
2020-05-04 |
Luke Kenneth Casso... | document PortInterface, start on "dummy" L0CacheBuffer |
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2020-05-04 |
Luke Kenneth Casso... | whitespace |
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2020-05-04 |
Luke Kenneth Casso... | better comments on rd/wr pending |
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2020-05-03 |
Luke Kenneth Casso... | move unused out of soc directory |
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