2021-11-19 |
Luke Kenneth Casso... | debug and cleanup |
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2021-11-19 |
Luke Kenneth Casso... | rename instruction_active to instr_active in core |
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2021-11-19 |
Luke Kenneth Casso... | read latch on regfile ports was fine, the combinatorial... |
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2021-11-19 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-11-19 |
Luke Kenneth Casso... | latch copy of read register numbers, not in use due... |
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2021-11-19 |
Luke Kenneth Casso... | use read spec in connect_rdport rather than list of... |
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2021-11-19 |
Luke Kenneth Casso... | capture write regfile numbers into write latches in... |
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2021-11-19 |
Luke Kenneth Casso... | code tidyup / comments, and use defaultdict |
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2021-11-19 |
Luke Kenneth Casso... | create lists of latches in each FU, to record the read... |
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2021-11-19 |
Luke Kenneth Casso... | for some reason DMI CTRL returns status of 0x6 not 0x0 |
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2021-11-19 |
Luke Kenneth Casso... | missing argument, domain="sync" in JTAG instance |
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2021-11-19 |
Luke Kenneth Casso... | return None if data returned is empty |
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2021-11-18 |
Luke Kenneth Casso... | remove combinatorial loop in core instruction conflict... |
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2021-11-18 |
Luke Kenneth Casso... | experimenting with overlapping instructions, bit of... |
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2021-11-18 |
Luke Kenneth Casso... | set up core processing FSM, which captures data if... |
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2021-11-18 |
Luke Kenneth Casso... | set up a temporary copy of CoreInput |
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2021-11-18 |
Luke Kenneth Casso... | experiment allowing overlap (activated with --allow... |
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2021-11-18 |
Luke Kenneth Casso... | remove unneeded import |
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2021-11-18 |
Tobias Platen | more work on test_loadstore1 |
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2021-11-17 |
Jacob Lifshay | start adding bitmanip FU |
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2021-11-17 |
Tobias Platen | PortInterfaceBase: fix fast exception handling |
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2021-11-17 |
Tobias Platen | whitespace |
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2021-11-17 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-11-17 |
Tobias Platen | fix mistake in test_pi2ls.py |
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2021-11-17 |
Luke Kenneth Casso... | reading of regfile bitvector added, which activates... |
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2021-11-17 |
Luke Kenneth Casso... | core hazard bitvector regfiles need to be readable |
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2021-11-17 |
Tobias Platen | fixed busy waiting in pi_st |
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2021-11-17 |
Luke Kenneth Casso... | add option to test_issuer.py to allow for overlapping... |
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2021-11-17 |
Luke Kenneth Casso... | add ability to run hazard instruction for test purposes |
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2021-11-17 |
Luke Kenneth Casso... | detect the case in Core bitvector when the Function... |
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2021-11-17 |
Luke Kenneth Casso... | add probe of whether CompUnit ALU is done or not. |
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2021-11-17 |
Luke Kenneth Casso... | missing optional check on make_hazard_vecs |
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2021-11-17 |
Luke Kenneth Casso... | move core hazard set/clear to separate function, for... |
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2021-11-17 |
Luke Kenneth Casso... | whoops context-indentation by mistake (no harm done... |
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2021-11-17 |
Luke Kenneth Casso... | add a FetchOutput pipeline data structure |
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2021-11-16 |
Luke Kenneth Casso... | print out regfile unary status, bit of name-cleanup |
tree | commitdiff |
2021-11-16 |
Luke Kenneth Casso... | use a virtual regfile port for the hazard bitvectors |
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2021-11-16 |
Tobias Platen | pi_ld busy waiting fix |
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2021-11-16 |
Tobias Platen | loadstore1 now reports exception reason |
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2021-11-16 |
Luke Kenneth Casso... | create set/get ports for bitvectors |
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2021-11-16 |
Luke Kenneth Casso... | capture write port (wrflag) in byregfiles_spec for... |
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2021-11-16 |
Luke Kenneth Casso... | rename regports for bitvectors so that |
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2021-11-16 |
Luke Kenneth Casso... | starting to get write-clear of hazard vectors operating |
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2021-11-16 |
Luke Kenneth Casso... | whoops, hazard vectors were depth 1 width N |
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2021-11-15 |
Tobias Platen | report dar on exception + test case |
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2021-11-15 |
Tobias Platen | add test_loadstore1.py |
tree | commitdiff |
2021-11-13 |
Luke Kenneth Casso... | add quick instructions on how to run pinouts.py to... |
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2021-11-13 |
Luke Kenneth Casso... | update submodule to make ngi pointer router pinouts |
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2021-11-13 |
Luke Kenneth Casso... | add new get_pinspec_resources function which creates... |
tree | commitdiff |
2021-11-13 |
Luke Kenneth Casso... | code-comment for get_pinspecs() |
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2021-11-13 |
Luke Kenneth Casso... | start adding hazard vector setting in core (unfinished) |
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2021-11-11 |
Luke Kenneth Casso... | debug prints |
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2021-11-11 |
Luke Kenneth Casso... | fix regfile port names for "fast" port access (regreduc... |
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2021-11-11 |
Luke Kenneth Casso... | TODO, implement is_dcbz |
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2021-11-11 |
Luke Kenneth Casso... | code-comments |
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2021-11-11 |
Luke Kenneth Casso... | split out core input/output into separate file core_data.py |
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2021-11-11 |
Luke Kenneth Casso... | enable hazard vecs in core |
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2021-11-11 |
Luke Kenneth Casso... | add exact same number - and name - bitvector ports... |
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2021-11-11 |
Luke Kenneth Casso... | code-morph regfile port specs to a dictionary format... |
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2021-11-11 |
Luke Kenneth Casso... | invert numbering on CR HDLState.get_crregs |
tree | commitdiff |
2021-11-10 |
Luke Kenneth Casso... | update store data reg 10 to 0xfe in virtmode mmu test |
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2021-11-10 |
Luke Kenneth Casso... | remove read of MSR, it is done by passing through Power... |
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2021-11-10 |
Luke Kenneth Casso... | allow MSR to be set in StateRegs in test_core.py |
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2021-11-10 |
Luke Kenneth Casso... | add $Display of oper_r.msr in LDSTCompUnit |
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2021-11-10 |
Luke Kenneth Casso... | whitespace |
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2021-11-10 |
Luke Kenneth Casso... | morph regfiles to add hazard vector make_vecs function |
tree | commitdiff |
2021-11-10 |
Luke Kenneth Casso... | add fetch of MSR in LD/ST pipe_data |
tree | commitdiff |
2021-11-10 |
Tobias Platen | add debug output for msr_pr |
tree | commitdiff |
2021-11-10 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-11-10 |
Tobias Platen | test testcase for exception |
tree | commitdiff |
2021-11-10 |
Luke Kenneth Casso... | make core busy_o part of the CoreOutput data structure |
tree | commitdiff |
2021-11-10 |
Luke Kenneth Casso... | add a "fu_found" signal to core, which allows for an... |
tree | commitdiff |
2021-11-09 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-11-09 |
Tobias Platen | test_issuer_mmu.py: add case_5_allsprs |
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2021-11-09 |
Luke Kenneth Casso... | add core instruction-issue PriorityPickers |
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2021-11-09 |
Luke Kenneth Casso... | comments |
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2021-11-09 |
Luke Kenneth Casso... | core.py: create a dictionary of lists of Function Units... |
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2021-11-09 |
Luke Kenneth Casso... | create function core conect_satellite_decoders |
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2021-11-09 |
Luke Kenneth Casso... | add cancel in to alu_ok / alu_valid in LDSTCompUnit |
tree | commitdiff |
2021-11-09 |
Luke Kenneth Casso... | rename LDSTCompUnit cancel to canceln (because it is... |
tree | commitdiff |
2021-11-09 |
Luke Kenneth Casso... | whoops must remember to do rdmaskn on LDSTCompUnit... |
tree | commitdiff |
2021-11-08 |
Luke Kenneth Casso... | remove unit test that is unfinished |
tree | commitdiff |
2021-11-08 |
Luke Kenneth Casso... | shorter way of getting FU busy signals |
tree | commitdiff |
2021-11-08 |
Luke Kenneth Casso... | MultiCompUnit fixed to not need rdmask to be sustained... |
tree | commitdiff |
2021-11-08 |
Luke Kenneth Casso... | in MultiCompUnit, put rdmaskn into src latch rather... |
tree | commitdiff |
2021-11-08 |
Tobias Platen | mmu unit test working again |
tree | commitdiff |
2021-11-08 |
Luke Kenneth Casso... | remove unused variable |
tree | commitdiff |
2021-11-08 |
Luke Kenneth Casso... | code comments |
tree | commitdiff |
2021-11-08 |
Luke Kenneth Casso... | comments |
tree | commitdiff |
2021-11-08 |
Luke Kenneth Casso... | remove issue_i from core, use i_valid instead to decide... |
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2021-11-08 |
Luke Kenneth Casso... | move "exception happened" detection from TestIssuer... |
tree | commitdiff |
2021-11-08 |
Luke Kenneth Casso... | use p.i_valid in core instead of explicit signal ivalid_i |
tree | commitdiff |
2021-11-08 |
Luke Kenneth Casso... | use Pipeline API o_ready instead of explicit core busy_... |
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2021-11-08 |
Luke Kenneth Casso... | convert core.py to Pipeline API, deriving from ControlBase |
tree | commitdiff |
2021-11-08 |
Luke Kenneth Casso... | remove unneeded imports |
tree | commitdiff |
2021-11-08 |
Luke Kenneth Casso... | move simple core input and output data to in/out data... |
tree | commitdiff |
2021-11-07 |
Luke Kenneth Casso... | make FSMDivCoreStage properly conform to Stage API |
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2021-11-07 |
Luke Kenneth Casso... | add hazard vectors to Regfiles |
tree | commitdiff |
2021-11-07 |
Luke Kenneth Casso... | add quick test of regfiles to output rtlil |
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2021-11-07 |
Luke Kenneth Casso... | switch over to single-entry (num_rows=1) ReservationSta... |
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