mem: Allocate cache writebacks before new MSHRs
[gem5.git] / src /
2015-03-27 Andreas Hanssonmem: Allocate cache writebacks before new MSHRs
2015-03-27 Andreas Hanssonmem: Cleanup flow for uncacheable accesses
2015-03-27 Andreas Hanssonmem: Ignore uncacheable MSHRs when finding matches
2015-03-27 Andreas Hanssonmem: Remove redundant allocateUncachedReadBuffer in...
2015-03-27 Andreas Hanssonmem: Modernise MSHR iterators to C++11
2015-03-27 Andreas Hanssonmem: Align all MSHR entries to block boundaries
2015-03-27 Ali Jafrimem: Rename PREFETCH_SNOOP_SQUASH flag to BLOCK_CACHED
2015-03-26 Curtis Dunhamsim: Update limit_event reuse to final version
2015-03-26 Andreas Hanssoncpu: Fix InstPBTrace inheritance
2015-03-23 Steve Reinhardtmem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW
2015-03-23 Steve Reinhardtmisc: quote args in echoed command line
2015-03-23 Curtis Dunhamsim: Reuse the same limit_event in simulate()
2015-03-23 Andreas Hanssonmem: Tidy up Request
2015-03-19 Matt Evansarm: Add a GICv2m device
2015-03-19 Matt Evansarm: Remove the 'magic MSI register' in the GIC (PL390)
2015-03-19 Wendy Elsassercpu: Fix TrafficGen message format
2015-03-19 Andreas Hanssonmem: Use emplace front/back for deferred packets
2015-03-19 Geoffrey Blakemem: Enable CommMonitor to output traces in atomic...
2015-02-11 Steve Reinhardtmem: remove redundant test in in Cache::recvTimingResp()
2015-02-11 Steve Reinhardtmem: add local var in Cache::recvTimingResp()
2015-02-11 Steve Reinhardtmem: restructure Packet cmd initialization a bit more
2015-03-14 Steve Reinhardtmem: clean up write buffer check in Cache::handleSnoop()
2015-03-09 Nilay Vaishcpu: o3: another assert instead of check
2015-03-09 Nilay Vaishcpu: o3: Remove unused code in iew, add assert instead.
2015-03-09 Nilay Vaishcpu: o3: commit: mark pipeline delay variable as consts
2015-03-09 Nilay Vaishcpu: o3: remove unused stat variables.
2015-03-09 Nilay Vaishcpu: o3: combine if with same condition
2015-03-09 Nilay Vaishcpu: o3: remove member variable squashCounter
2015-03-09 Nilay Vaishcpu: o3: remove unused function annotateMemoryUnits()
2015-03-02 Andreas Hanssonmem: Unify all cache DPRINTF address formatting
2015-03-02 Andreas Hanssonmem: Fix cache MSHR conflict determination
2015-03-02 Andreas Hanssonmem: Add byte mask to Packet::checkFunctional
2015-03-02 Stephan Diestelhorstmem: Add option to force in-order insertion in PacketQueue
2015-03-02 Marco Balbonimem: Downstream components consumes new crossbar delays
2015-03-02 Andreas Hanssonmem: Move crossbar default latencies to subclasses
2015-03-02 Marco Balbonimem: Add crossbar latencies
2015-03-02 Andreas Sandbergdev, arm: Clean up PL011 and rewrite interrupt handling
2015-03-02 Andreas Hanssonarm: Share a port for the two table walker objects
2015-03-02 Giacomo Gabrielliarm: Remove unnecessary dependencies between AArch64...
2015-03-02 Rekaicpu: o3 register renaming request handling improved
2015-03-02 Andreas Hanssonmem: Tidy up the cache debug messages
2015-03-02 Andreas Hanssonmem: Split port retry for all different packet classes
2015-03-02 Ali Jafrimem: Fix prefetchSquash + memInhibitAsserted bug
2015-03-02 Stephan Diestelhorstcpu: Add a PC-value to the traffic generator requests
2015-03-02 Andreas Sandbergarm: Don't truncate 16-bit ASIDs to 8 bits
2015-03-02 Andreas Sandbergarm: Correctly access the stack pointer in GDB
2015-03-02 Andreas Sandbergarm: Fix broken page table permissions checks in remote GDB
2015-02-26 Jason PowerRuby: Update backing store option to propagate through...
2015-02-16 Andreas Hanssoncpu: TrafficGen sinks snoops without complaining
2015-02-16 Stephan Diestelhorstmem: Fix initial value problem with MemChecker
2015-02-16 Andreas Hanssondev: Fix undefined behaviuor in i8254xGBe
2015-02-16 Andreas Sandbergarm: Wire up the GIC with the platform in the base...
2015-02-16 Andreas Hanssonmem: mmap the backing store with MAP_NORESERVE
2015-02-16 Andreas Hanssonmem: Use the range cache for lookup as well as access
2015-02-16 Andreas Hanssonarch: Make readMiscRegNoEffect const throughout
2015-02-16 Andreas Sandbergarm: Merge ISA files with pseudo instructions
2015-02-16 Ali Saidicpu: add support for outputing a protobuf formatted...
2015-02-11 Marco Balbonimem: Clarification of packet crossbar timings
2015-02-11 Marco Balbonimem: Clarify usage of latency in the cache
2015-02-11 Andreas Hanssoncpu: Tidy up the MemTest and make false sharing more...
2015-02-11 Andreas Sandbergsim: Move the BaseTLB to src/arch/generic/
2015-02-11 Andreas Sandbergbase: Add compiler macros to add deprecation warnings
2015-02-11 Andreas Hanssonbase: Do not dereference NULL in CompoundFlag creation
2015-02-11 Andreas Sandbergdev: Remove unused system pointer in the Platform base...
2015-02-07 Alexandru Dutucpu: Idle CPU status logic revised
2015-02-03 Andreas Hanssonmem: Clarify express snoop behaviour
2015-02-03 Andreas Hanssonmem: Clarify cache behaviour for pending dirty responses
2015-02-03 Curtis Dunhambase: add an accessor and operators ==,!= to address...
2015-02-03 Andreas Hanssonbase: Add XOR-based hashed address interleaving
2015-02-03 Andreas Hanssonconfig: Adjust DRAM channel interleaving defaults
2015-02-03 Andreas Sandbergsim: Remove test for non-NULL this in Event
2015-02-03 Andreas Sandbergdev: Correctly clear interrupts in VirtIO PCI
2014-12-19 Curtis Dunhamsim: prioritize async events; prevent starvation
2015-02-03 Andreas Hanssoncpu: Ensure timing CPU sinks response before sending...
2015-02-03 Geoffrey Blakeconfig: Fix typo in Float param
2015-01-25 Ali Saidiarm: always set the IsFirstMicroop flag
2015-01-25 Ali Saidisim: Clean up InstRecord
2015-01-25 Ali Saidicpu: Remove all notion that we know when the cpu is...
2015-01-25 Ali Saidicpu: Put all CPU instruction tracers in a single file
2015-01-25 Ali Saidicpu: remove legion tracer
2014-12-23 Curtis Dunhamsim: fix reference counting of PythonEvent
2015-01-22 Andreas Hanssonmem: Remove unused Packet src and dest fields
2015-01-22 Andreas Hanssonmem: Remove Packet source from ForwardResponseRecord
2015-01-22 Andreas Hanssonmem: Remove unused RequestState in the bridge
2015-01-22 Andreas Hanssonmem: Always use SenderState for response routing in...
2015-01-22 Andreas Hanssonmem: Make the XBar responsible for tracking response...
2015-01-22 Andreas Hanssonx86: Delay X86 table walk on receiving walker response
2015-01-22 Andreas Hanssonmem: Clean up Request initialisation
2015-01-20 Nikos Nikoleriscpu: commit probe notification on every microop or...
2015-01-20 Andreas Hanssonmem: Fix bug in cache request retry mechanism
2015-01-20 Andreas Hanssoncpu: Fix retry bug in MinorCPU LSQ
2015-01-20 Andreas Hanssonmem: Move DRAM interleaving check to init
2015-01-10 Emilio Castillox86 : fxsave and fxrestore missing template code
2015-01-10 Nikos Nikoleriscpu: fix RetiredStores probe point
2015-01-06 cdirikdev: prevent intel 8254 timer counter events firing...
2015-01-07 Gabe Blacktest: Add a unittest for the BitUnion types.
2015-01-07 Gabe Blackbase: Fix assigning between identical bitfields.
2015-01-07 Gabe Blackx86: Enable three bits in the FamilyModelStepping ECX...
2015-01-07 Gabe Blackcpuid, x86: Revert "Enabling more features in CPUid"
2015-01-03 Andrew Lukefahrminor: fixed LSQ MasterPortID
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