cpu: `Minor' in-order CPU model
[gem5.git] / src /
2014-07-23 Andrew Bardsleycpu: `Minor' in-order CPU model
2014-07-19 Steve Reinhardtsyscall emulation: fix fast build issue
2014-07-19 Binh Phamx86: make PioBus return BadAddress errors
2014-07-19 Steve Reinhardtsim: remove unused MemoryModeStrings array
2014-07-19 Steve Reinhardtkern: get rid of unused linux syscall files
2014-07-19 Steve Reinhardtsyscall emulation: fix DPRINTF arg ordering bug
2014-07-09 Anthony Gutierrezbase: fix operator== for comparing EthAddr objects
2014-07-02 Anthony Gutierrezbase: fix some bugs in EthAddr
2014-07-01 Radhika Jagtaputil: Add DVFS perfLevel to checkpoint upgrade script
2014-06-30 Stephan Diestelhorstpower: Add basic DVFS support for gem5
2014-06-30 Andreas Hanssonmem: DRAMPower trace output
2014-06-30 Andreas Hanssonmem: Add bank and rank indices as fields to the DRAM...
2014-06-30 Andreas Hanssonmem: Extend DRAM row bits from 16 to 32 for larger...
2014-06-30 Anthony Gutierrezcpu: implement a bi-mode branch predictor
2014-06-21 Binh Phamx86: fix table walker assertion
2014-06-21 Binh Phamo3: make dispatch LSQ full check more selective
2014-06-21 Binh Phamo3: split load & store queue full cases in rename
2014-06-10 Andreas Hanssonscons: Bump the compiler version to gcc 4.6 and clang 3.0
2014-06-10 Joel Hestnesssim: More rigorous clocking comments
2014-06-01 Steve Reinhardtstyle: eliminate equality tests with true and false stable_2014_08_26
2014-05-23 Nilay Vaishruby: slicc: remove unused ids DNUCA*
2014-05-23 Nilay Vaishruby: remove old protocol documentation
2014-05-23 Nilay Vaishruby: message buffer: drop dequeue_getDelayCycles()
2014-05-23 Nilay Vaishcpu: o3: remove stat totalCommittedInsts
2014-05-12 Steve Reinhardtsyscall emulation: clean up & comment SyscallReturn
2014-05-09 Andreas Hanssonmem: Update DDR3 and DDR4 based on datasheets
2014-05-09 Andreas Hanssonmem: Add DRAM cycle time
2014-05-09 Andreas Hanssonmem: Simplify DRAM response scheduling
2014-05-09 Andreas Hanssonmem: Add precharge all (PREA) to the DRAM controller
2014-05-09 Andreas Hanssonmem: Remove printing of DRAM params
2014-05-09 Andreas Hanssonmem: Add tRTP to the DRAM controller
2014-05-09 Andreas Hanssonmem: Merge DRAM latency calculation and bank state...
2014-05-09 Andreas Hanssonmem: Add tWR to DRAM activate and precharge constraints
2014-05-09 Andreas Hanssonmem: Merge DRAM page-management calculations
2014-05-09 Andreas Hanssonmem: Add DRAM power states to the controller
2014-05-09 Andreas Hanssonmem: Ensure DRAM refresh respects timings
2014-05-09 Andreas Hanssonmem: Make DRAM read/write switching less conservative
2014-04-17 Ali Saidiarm: Make sure UndefinedInstructions are properly initi...
2014-04-17 Ali Saidiarm: allow DC instructions by default so SE mode works
2014-04-17 Ali Saidisim, arm: implement more of the at variety syscalls
2014-05-09 Andrew Bardsleycpu: Useful getters for ActivityRecorder
2014-05-09 Andrew Bardsleycpu: Add flag name printing to StaticInst
2014-05-09 Andrew Bardsleycpu: Timebuf const accessors
2014-05-09 Andrew Bardsleyarm: Add branch flags onto macroops
2014-05-09 Andrew Bardsleycpu: Allow setWhen on trace objects
2014-05-09 Curtis Dunhamarm: add preliminary ISA splits for ARM arch
2014-05-09 Curtis Dunhamarch: teach ISA parser how to split code across files
2014-05-09 Geoffrey Blakeconfig: Avoid generating a reference to myself for...
2014-05-09 Geoffrey Blakearch, arm: Preserve TLB bootUncacheability when switchi...
2014-05-09 Curtis Dunhamcpu: add more instruction mix statistics
2014-05-09 Mitch Hayengamem: Squash prefetch requests from downstream caches
2014-05-09 Stephan Diestelhorststats: Method stats source
2014-05-09 Akash Bagdiacpu, arm: Allow the specification of a socket field
2014-05-09 Sascha Bischoffmem: Auto-generate CommMonitor trace file names
2014-05-09 Geoffrey Blakearm: Panics in miscreg read functions can be tripped...
2014-05-09 Chris Emmonsdev: Set HDLCD default pixel clock for 1080p @ 60Hz
2014-05-09 Matt Evansarm: quick hack to allow a greater number of CPUs to...
2014-05-09 Curtis Dunhamarch: remove inline specifiers on all inst constrs...
2014-05-09 Curtis Dunhamarm: cleanup ARM ISA definition
2014-05-09 Curtis Dunhamscons: Require SWIG >= 2.0.4 and remove vector typemaps
2014-04-23 Curtis Dunhamarm: Correctly display disassembly of vldmia/vstmia
2014-04-23 Andreas Hanssonsim: Use correct unit for abort message
2014-04-23 Mitchell Hayengacpu: Fix setTranslateLatency() bug for squashed instruc...
2014-04-23 Sascha Bischoffmisc: Proper type check and import for PortRef
2014-04-01 Mitch Hayengacpu: Fix case where o3 lsq could print out uninitialize...
2014-04-01 Mitch Hayengamem: Don't print out the data of a cache block
2014-04-23 Mitchell Hayengaarm: Don't use a stack allocated mnemonic
2014-04-23 Dam Sunwoocpu: Add O3 CPU width checks
2014-04-23 Curtis Dunhambase: explicitly suggest potential use of 'All' debug...
2014-04-23 Curtis Dunhamarch: remove 'null update' check in isa-parser
2014-02-11 Curtis Dunhamstats: better error message for uninitialized statistic
2014-04-19 Nilay Vaishruby: slicc: remove old documentation
2014-04-19 Nilay Vaishruby: slicc: slight change to rule for transitions
2014-04-19 Faissal Sleimano3: Fix occupancy checks for SMT
2014-04-19 Marco Elverruby: recorder: Fix (de-)serializing with different...
2014-04-09 Andreas Sandbergkvm, x86: Add initial support for multicore simulation
2014-04-09 Andreas Sandbergdev: Protect PollEvent processing when running in paral...
2014-04-08 Nilay Vaishruby: slicc: change enqueue statement
2014-04-08 Nilay Vaishruby: coherence protocols: drop the phrase IntraChip
2014-04-03 Andreas Sandbergsim: Add the ability to lock and migrate between event...
2014-03-25 Marco Elvercpu: o3: lsq: Fix TSO implementation
2014-03-23 Andreas Hanssonmem: Track DRAM read/write switching and add hysteresis
2014-03-23 Andreas Hanssonmem: Rename SimpleDRAM to a more suitable DRAMCtrl
2014-03-23 Andreas Hanssonmem: Change memory defaults to be more representative
2014-03-23 Wendy Elsassermem: Add close adaptive paging policy to DRAM controlle...
2014-03-23 Andreas Hanssonmem: DRAM controller tidying up
2014-03-23 Andreas Hanssonmem: Fix bug in DRAM bytes per activate
2014-03-23 Andreas Hanssonmem: Limit the accesses to a page before forcing a...
2014-03-23 Andreas Hanssonmem: Make DRAM write queue draining more aggressive
2014-03-23 Neha Agarwalcpu: DRAM Traffic Generator
2014-03-23 Neha Agarwalmem: DDR3 config for comparing with DRAMSim2
2014-03-23 Andreas Hanssonmem: More descriptive address-mapping scheme names
2014-03-23 Stan Czerniawskimisc: Fix -q (quiet) flag
2014-03-23 Andreas Hanssonruby: Move Ruby debug flags to ruby dir and remove...
2014-03-23 Andreas Hanssonmem: Include the DRAMSim2 wrapper in NULL build
2014-03-23 Sascha Bischoffmem: CommMonitor trace warn on non-timing mode
2014-03-23 Stan Czerniawskicpu: Add basic check to TrafficGen initial state
2014-03-23 Andrew Bardsleydev: Fix IsaFake's cxx_header setting
2014-03-23 Eric Van Hensbergenarm: m5ops readfile64 args broken, offset coming throug...
2014-03-23 Andreas Hanssonbase: Fix error message time unit (cycle -> tick)
next