2021-12-13 |
Luke Kenneth Casso... | still have to import MSRSpec |
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2021-12-13 |
Luke Kenneth Casso... | connect up PortInterface priv_mode, virt_mode and mode_... |
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2021-12-13 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-12-13 |
Luke Kenneth Casso... | construct an MSRSpec in PortInterfaceBase (not used... |
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2021-12-13 |
Tobias Platen | remove redundant MSRSpec from pimem |
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2021-12-13 |
Luke Kenneth Casso... | whoops wrong variable names |
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2021-12-13 |
Luke Kenneth Casso... | rename msr_pr to priv_mode in LDSTCompUnit |
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2021-12-13 |
Luke Kenneth Casso... | TODO comments about using MSRspec |
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2021-12-13 |
Luke Kenneth Casso... | change PortInterface naming to msr not msr_pr in set_wr... |
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2021-12-13 |
Tobias Platen | add namedtuple proposed by lkcl in chat |
tree | commitdiff |
2021-12-13 |
Tobias Platen | add signals to port interface as descibed in bug 756 |
tree | commitdiff |
2021-12-13 |
Tobias Platen | more work on test_loadstore1_ifetch_multi() |
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2021-12-12 |
Luke Kenneth Casso... | set and reset instruction fault so it does not occur... |
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2021-12-12 |
Luke Kenneth Casso... | when an exception happens, if it is a fetch_failed... |
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2021-12-12 |
Luke Kenneth Casso... | delay MMU LOOKUP done by one clock so that the exceptio... |
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2021-12-12 |
Luke Kenneth Casso... | bring MMU exception out where AllFunctionUnits (and... |
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2021-12-12 |
Luke Kenneth Casso... | bring exception out from MMU FSM, correct "done" |
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2021-12-12 |
Luke Kenneth Casso... | add LDSTException output to MMU |
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2021-12-12 |
Luke Kenneth Casso... | drat, a test inverting the instruction made it into... |
tree | commitdiff |
2021-12-12 |
Luke Kenneth Casso... | starting to hack in fetch failed (including OP_FETCH_FA... |
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2021-12-12 |
Luke Kenneth Casso... | print debugs established that when a wb_get memory... |
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2021-12-12 |
Luke Kenneth Casso... | set fetch_failed into PowerDecoder2 combinatorially |
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2021-12-12 |
Luke Kenneth Casso... | in a terrible botched way, get at I-Cache and set it up |
tree | commitdiff |
2021-12-11 |
Luke Kenneth Casso... | fix bug in unit test, forgot that wb_get mem dict is... |
tree | commitdiff |
2021-12-11 |
Luke Kenneth Casso... | get FetchUnitInterface I-Cache test working (sort-of) |
tree | commitdiff |
2021-12-11 |
Luke Kenneth Casso... | comment out broken test |
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2021-12-11 |
Luke Kenneth Casso... | whoops forgot to add pspec |
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2021-12-11 |
Tobias Platen | typo fix, add missing stop statement to _test_loadstore... |
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2021-12-11 |
Tobias Platen | add loop with multiple instructions for testing |
tree | commitdiff |
2021-12-11 |
Tobias Platen | add skeleton for test_loadstore1_ifetch_multi() |
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2021-12-11 |
Luke Kenneth Casso... | add start of test_loadstore1_ifetch_unit_interface() |
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2021-12-11 |
Luke Kenneth Casso... | connect up I-Cache to FetchUnitInterface |
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2021-12-11 |
Luke Kenneth Casso... | add new ConfigFetchUnit option "mmu_cache_wb" which... |
tree | commitdiff |
2021-12-10 |
Jacob Lifshay | add ternlogi to shift_rot formal test |
tree | commitdiff |
2021-12-10 |
Jacob Lifshay | fix shift_rot formal proof |
tree | commitdiff |
2021-12-10 |
Tobias Platen | use icache_read in one place |
tree | commitdiff |
2021-12-10 |
Tobias Platen | test_loadstore1.py: begin code deduplication |
tree | commitdiff |
2021-12-09 |
Luke Kenneth Casso... | add some examination of the failed-fetched instruction |
tree | commitdiff |
2021-12-09 |
Luke Kenneth Casso... | add some debug string info to gtkwave |
tree | commitdiff |
2021-12-09 |
Tobias Platen | implement main part of test_loadstore1_ifetch_invalid() |
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2021-12-09 |
Tobias Platen | cleanup test_loadstore1.py |
tree | commitdiff |
2021-12-09 |
Luke Kenneth Casso... | add I-Cache to FSM local variables |
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2021-12-09 |
Luke Kenneth Casso... | wire fetch_failed from I-Cache to PowerDecoder2 |
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2021-12-09 |
Luke Kenneth Casso... | make icache accessible to core, working back to TestIssuer |
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2021-12-09 |
Luke Kenneth Casso... | include SPR.TB in SPR FU |
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2021-12-09 |
Jacob Lifshay | add bitmanip tests |
tree | commitdiff |
2021-12-09 |
Jacob Lifshay | add CommonPipeSpec.__getattr__ to forward attributes... |
tree | commitdiff |
2021-12-09 |
Jacob Lifshay | add parent_pspec everywhere |
tree | commitdiff |
2021-12-09 |
Jacob Lifshay | make argv handling more flexible |
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2021-12-09 |
Jacob Lifshay | format code |
tree | commitdiff |
2021-12-08 |
Luke Kenneth Casso... | got fed up of staring at magic constants in the MMU |
tree | commitdiff |
2021-12-08 |
Luke Kenneth Casso... | add special pagetable to ifetch_invalid with execute... |
tree | commitdiff |
2021-12-08 |
Luke Kenneth Casso... | do not try priv_mode on the instruction fetch (not... |
tree | commitdiff |
2021-12-08 |
Luke Kenneth Casso... | add an example pagetable where executable permission... |
tree | commitdiff |
2021-12-08 |
Tobias Platen | begin working on _test_loadstore1_ifetch_invalid()... |
tree | commitdiff |
2021-12-08 |
Tobias Platen | more work on test_loadstore1_ifetch_invalid() |
tree | commitdiff |
2021-12-08 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-12-08 |
Tobias Platen | add skeleton for test_loadstore1_ifetch_invalid() |
tree | commitdiff |
2021-12-08 |
Luke Kenneth Casso... | check that no exception occurs in the virtual-memory... |
tree | commitdiff |
2021-12-08 |
Luke Kenneth Casso... | add OP_FETCH_FAILED to MMU Function Unit |
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2021-12-08 |
Luke Kenneth Casso... | make LoadStore1 intsr_fault a "captured flag" - strictl... |
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2021-12-08 |
Luke Kenneth Casso... | remove MSR and add CIA to MMU Input Record |
tree | commitdiff |
2021-12-08 |
Luke Kenneth Casso... | add instr_fault to LoadStore1 FSM |
tree | commitdiff |
2021-12-08 |
Luke Kenneth Casso... | add new PortInterfaceBase external_busy() option |
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2021-12-08 |
Jacob Lifshay | add comment about draft instructions |
tree | commitdiff |
2021-12-08 |
Jacob Lifshay | account for Mock absurdities |
tree | commitdiff |
2021-12-07 |
Luke Kenneth Casso... | complete the i-cache fetch through the MMU, including... |
tree | commitdiff |
2021-12-07 |
Luke Kenneth Casso... | set separate "iside" signal in LoadStore1 to not confuse it |
tree | commitdiff |
2021-12-07 |
Luke Kenneth Casso... | start extending icache loadstore test |
tree | commitdiff |
2021-12-07 |
Luke Kenneth Casso... | whoops another serious error in the CacheTagArray |
tree | commitdiff |
2021-12-07 |
Luke Kenneth Casso... | add first i-cache fetch (non-virtual), no MMU lookup... |
tree | commitdiff |
2021-12-07 |
Luke Kenneth Casso... | code-comments |
tree | commitdiff |
2021-12-07 |
Luke Kenneth Casso... | add in I-Cache into LoadStore1 - presently unused ... |
tree | commitdiff |
2021-12-07 |
Luke Kenneth Casso... | add discussion links and bugreport |
tree | commitdiff |
2021-12-07 |
Luke Kenneth Casso... | invert mmureq statements |
tree | commitdiff |
2021-12-07 |
Luke Kenneth Casso... | submodule tidyup |
tree | commitdiff |
2021-12-07 |
Jacob Lifshay | make bitmanip operations conditional on pspec.draft_bit... |
tree | commitdiff |
2021-12-07 |
Jacob Lifshay | format code |
tree | commitdiff |
2021-12-07 |
Jacob Lifshay | move rotator mode assignments as requested by lkcl |
tree | commitdiff |
2021-12-07 |
Jacob Lifshay | format code |
tree | commitdiff |
2021-12-07 |
Luke Kenneth Casso... | tidyup, comments |
tree | commitdiff |
2021-12-07 |
Luke Kenneth Casso... | debug print |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | another major bug, CacheTagArray valid was only 1 bit... |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | tidyup: move hit_set to DCachePendingHit in dcache.py |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | dcache.py tidyup |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | rename dtlb to dtlb_valid and tidyup |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | convert TLBArray to TLBValidArray |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | convert DTLBUpdate to use a pair of Memorys |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | more signals local to DTLBUpdate |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | more signals local to DTLBUpdate |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | update DTLBUpdate to reflect internal API now |
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2021-12-06 |
Luke Kenneth Casso... | ooo nasty bug. used tlb_hit.way instead of tlb_hit... |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | move DTLB Tags/Valids/PTEs into DTLBUpdate module |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | start moving TLBArray into DTLBUpdate |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | PLRUs were selecting an output index, only one selected |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | repeated copies of read/write addr/sel to Cache SRAMs |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | move bank of PLRUs to their own submodule in both dcach... |
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2021-12-06 |
Luke Kenneth Casso... | code-comments |
tree | commitdiff |
2021-12-06 |
Luke Kenneth Casso... | use binary-to-unary encoders in dcache.py |
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2021-12-06 |
Luke Kenneth Casso... | global (one) do_read signal in cache_rams dcache.py |
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