2019-02-13 |
Andreas Sandberg | python: Replace deprecated repr syntax |
tree | commitdiff |
2019-02-13 |
Andreas Sandberg | python: Switch from using compare to key in list sort |
tree | commitdiff |
2019-02-13 |
Ayaz Akram | sim-se: update the arm kernel version |
tree | commitdiff |
2019-02-12 |
Andreas Sandberg | python: Replace dict.has_key with 'key in dict' |
tree | commitdiff |
2019-02-12 |
Andreas Sandberg | python: Add missing defines import |
tree | commitdiff |
2019-02-12 |
Andreas Sandberg | python: Replace DictMixin with Mapping / MutableMapping |
tree | commitdiff |
2019-02-12 |
Andreas Sandberg | python: Replace orderdict with collections.OrderedDict |
tree | commitdiff |
2019-02-12 |
Andreas Sandberg | python: Update use of exec to work with Python 3 |
tree | commitdiff |
2019-02-12 |
Andreas Sandberg | python: Switch to using open instead of file |
tree | commitdiff |
2019-02-12 |
Javier Bueno | mem-cache: Irregular Stream Buffer Prefetcher |
tree | commitdiff |
2019-02-12 |
Javier Bueno | mem-cache: Added the Delta Correlating Prediction Table... |
tree | commitdiff |
2019-02-12 |
Andreas Sandberg | python: Don't assume SimObjects live in the global... |
tree | commitdiff |
2019-02-12 |
Andreas Sandberg | arch-mips: Remove unused Python file |
tree | commitdiff |
2019-02-12 |
Andreas Sandberg | python: Make exception handling Python 3 safe |
tree | commitdiff |
2019-02-12 |
Andreas Sandberg | python: Fix native module initialisation on Python 3 |
tree | commitdiff |
2019-02-12 |
Pouya Fotouhi | mem-ruby: Fixing Topology |
tree | commitdiff |
2019-02-12 |
Pouya Fotouhi | mem-ruby: Fixing MESI Three Level |
tree | commitdiff |
2019-02-11 |
Gabe Black | systemc: Change the type of a loop counter to avoid... |
tree | commitdiff |
2019-02-11 |
Gabe Black | scons: Change an = to a += when accumulating sources... |
tree | commitdiff |
2019-02-11 |
Gabe Black | systemc: scons: Specify RPATH as a list. |
tree | commitdiff |
2019-02-08 |
Jairo Balart | cpu: Proposal for changing the indirect branch predicto... |
tree | commitdiff |
2019-02-08 |
Tuan Ta | riscv: fix AMO, LR and SC instructions |
tree | commitdiff |
2019-02-08 |
Tuan Ta | cpu: support atomic memory request type with AtomicOpFu... |
tree | commitdiff |
2019-02-08 |
Moyang Wang | kern,sim: implement FUTEX_WAKE_OP |
tree | commitdiff |
2019-02-08 |
Moyang Wang | sim, kern: support FUTEX_CMP_REQUEUE |
tree | commitdiff |
2019-02-08 |
Tuan Ta | sim: handle the case when there're not enough HW thread... |
tree | commitdiff |
2019-02-08 |
Tuan Ta | riscv: fixed syscall return value |
tree | commitdiff |
2019-02-08 |
Tuan Ta | cpu: fix how branching is handled when a thread is... |
tree | commitdiff |
2019-02-08 |
Tuan Ta | cpu: stop scheduling suspended threads in all stages... |
tree | commitdiff |
2019-02-08 |
Tuan Ta | riscv: ignore nanosleep syscall |
tree | commitdiff |
2019-02-08 |
Tuan Ta | sim,cpu: make exit_group halt all threads in a group |
tree | commitdiff |
2019-02-08 |
Tuan Ta | arch-riscv: initialize RISC-V's thread pointer register... |
tree | commitdiff |
2019-02-08 |
Tuan Ta | sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITS... |
tree | commitdiff |
2019-02-08 |
Tuan Ta | cpu: fixed how O3 CPU executes an exit system call |
tree | commitdiff |
2019-02-08 |
Giacomo Travaglini | arch-arm: Fix Virtual interrupts in AArch64 |
tree | commitdiff |
2019-02-08 |
Giacomo Travaglini | arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72... |
tree | commitdiff |
2019-02-08 |
Giacomo Travaglini | arch-arm: Allow ArmPPI usage for PMU |
tree | commitdiff |
2019-02-08 |
Ruben Ayrapetyan | arch-arm: Fix initialization of PMU counters |
tree | commitdiff |
2019-02-07 |
Giacomo Travaglini | configs, arch-arm: Using AddrRange for Realview mem_regions |
tree | commitdiff |
2019-02-07 |
Austin Harris | arch-riscv: Enable support for riscv 32-bit in SE mode. |
tree | commitdiff |
2019-02-06 |
Tuan Ta | riscv: remove NonSpeculative flag from fence inst |
tree | commitdiff |
2019-02-06 |
Tuan Ta | cpu: fix how a thread starts up in MinorCPU |
tree | commitdiff |
2019-02-06 |
Tuan Ta | arch-riscv: Initialize interrupt mask |
tree | commitdiff |
2019-02-06 |
Ciro Santilli | scons: fix unused auto-generated blob variable in clang |
tree | commitdiff |
2019-02-06 |
Andrea Mondelli | sim: added missed macro definition on MacOS |
tree | commitdiff |
2019-02-05 |
Andrea Mondelli | misc: added missing override specifier |
tree | commitdiff |
2019-02-05 |
Javier Bueno | cpu: Made the Loop Predictor a SimObject |
tree | commitdiff |
2019-02-05 |
Jairo Balart | cpu: Made TAGE a SimObject that can be used by other... |
tree | commitdiff |
2019-02-05 |
Austin Harris | riscv: Get rid of ISA specific register types in Interr... |
tree | commitdiff |
2019-02-01 |
Javier Bueno | mem-cache: Updated version of the Signature Path Prefetcher |
tree | commitdiff |
2019-02-01 |
Anouk Van Laer | dev, arm: Removed contextId variable |
tree | commitdiff |
2019-02-01 |
Gabe Black | cpu, arch: Replace the CCReg type with RegVal. |
tree | commitdiff |
2019-01-31 |
Andreas Sandberg | python: Remove getCode() type workaround |
tree | commitdiff |
2019-01-31 |
Andreas Sandberg | sim: Prepare C++ side for Python 3 |
tree | commitdiff |
2019-01-31 |
Gabe Black | power: Get rid of some ISA specific register types. |
tree | commitdiff |
2019-01-31 |
Gabe Black | null: Get rid of some register type definitions. |
tree | commitdiff |
2019-01-31 |
Gabe Black | mips: Stop using architecture specific register types. |
tree | commitdiff |
2019-01-31 |
Gabe Black | alpha: Stop using architecture specific register types. |
tree | commitdiff |
2019-01-31 |
Gabe Black | x86: Stop using/defining some ISA specific register... |
tree | commitdiff |
2019-01-31 |
Gabe Black | riscv: Get rid of some ISA specific register types. |
tree | commitdiff |
2019-01-31 |
Gabe Black | arch: cpu: Rename *FloatRegBits* to *FloatReg*. |
tree | commitdiff |
2019-01-30 |
Giacomo Gabrielli | arch,cpu: Add vector predicate registers |
tree | commitdiff |
2019-01-30 |
Giacomo Travaglini | arch-arm, configs: Create single instance of DTB autoge... |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch-arm: Remove floatReg operand type |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch-arm: Use VecElem instead of FloatReg for FP instru... |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch: Fix VecElem Operand generation in ISA parser |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | cpu, arch, arch-arm: Wire unused VecElem code in the... |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | cpu: O3 rename using the flatIndex instead of index |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch-arm: Inital vector rename mode depending on A32/A64 |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | cpu: Fix VecElemClass bugs in cpu models |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | cpu: Add VecElem entries in MinorCPU Scoreboard |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch-arm: Remove unused float operands |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch: Provide traceback when parsing ISA code |
tree | commitdiff |
2019-01-25 |
Nicholas Lindsay | python: Always throw TypeError on slave-slave connections |
tree | commitdiff |
2019-01-24 |
Gabe Black | hsail: Remove the MiscReg type. |
tree | commitdiff |
2019-01-24 |
Gabe Black | base: arch: Get rid of the now unused FloatRegVal type. |
tree | commitdiff |
2019-01-24 |
Ciro Santilli | dev-arm: fix --generate-dtb for ARM |
tree | commitdiff |
2019-01-24 |
Rekai Gonzalez-Alb... | cpu-o3: O3 LSQ Generalisation |
tree | commitdiff |
2019-01-23 |
Giacomo Travaglini | arch-arm: Implement LoadAcquire/StoreRelease in AArch32 |
tree | commitdiff |
2019-01-23 |
Giacomo Travaglini | arch-arm: IsStoreConditional flag set depending on... |
tree | commitdiff |
2019-01-23 |
Giacomo Travaglini | arch-arm: Remove SWP and SWPB instructions |
tree | commitdiff |
2019-01-23 |
Gabe Black | systemc: Fix TLM related includes. |
tree | commitdiff |
2019-01-23 |
Gabe Black | arm: Replace MiscReg with RegVal in utility.(hh|cc). |
tree | commitdiff |
2019-01-23 |
Zicong Wang | mem-ruby: Fix missing TBE allocation and deallocation |
tree | commitdiff |
2019-01-22 |
Gabe Black | sparc: Get rid of some register type definitions. |
tree | commitdiff |
2019-01-22 |
Gabe Black | arch: cpu: Stop passing around misc registers by reference. |
tree | commitdiff |
2019-01-22 |
Gabe Black | arm: Get rid of some register type definitions. |
tree | commitdiff |
2019-01-22 |
Gabe Black | arm: dev: Replace ArmISA::MiscReg with RegVal in the... |
tree | commitdiff |
2019-01-22 |
Ciro Santilli | arch-arm: implement the GDB XML target description... |
tree | commitdiff |
2019-01-22 |
Ciro Santilli | scons: add helpers to access GDB XML description files |
tree | commitdiff |
2019-01-22 |
Ciro Santilli | scons: allow embedding arbitrary blobs into the gem5... |
tree | commitdiff |
2019-01-22 |
Ciro Santilli | base: add support for GDB's XML architecture definition |
tree | commitdiff |
2019-01-22 |
Giacomo Travaglini | arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers |
tree | commitdiff |
2019-01-22 |
Sascha Bischoff | mem: Add tryTiming suppport to CommMonitor |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se add readv and modifies writev |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se: add ability to get/set sock metadata |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se: add syscalls related to polling |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se: add calls for network transmissions |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se: add socket-based functionality |
tree | commitdiff |
2019-01-18 |
Daniel R. Carvalho | base: Fix unitialized storage |
tree | commitdiff |
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