2020-09-29 |
Cole Poirier | icache.py fix combinatorial loop with by testing temp... |
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2020-09-29 |
Cole Poirier | icache.py fix is_last_row_addr, get_next_row_addr |
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2020-09-29 |
Cole Poirier | icache.py trying to sort out test failure, added r... |
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2020-09-29 |
Cole Poirier | icache.py fix test stbs_done signal, not stbs_zero... |
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2020-09-29 |
Cole Poirier | icache.py fix rarange |
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2020-09-29 |
Cole Poirier | icache.py fixed numerous bugs as specified by lkcl... |
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2020-09-28 |
Cole Poirier | icache.py use d_out as input to assignment instead... |
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2020-09-28 |
Luke Kenneth Casso... | reduce not-connected IO pins |
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2020-09-28 |
Luke Kenneth Casso... | missing pspec |
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2020-09-28 |
Luke Kenneth Casso... | connect SDRAM dqm to wrdata_mask |
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2020-09-28 |
Luke Kenneth Casso... | lots of sorting out iopads |
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2020-09-28 |
Luke Kenneth Casso... | add "nocore" option to build verilog |
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2020-09-28 |
Luke Kenneth Casso... | switch off internal gpio (testing) |
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2020-09-28 |
Luke Kenneth Casso... | rewrite ilang file after litex ls180 build |
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2020-09-28 |
Luke Kenneth Casso... | had to over-ride the wishbone functions on C4M TAP |
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2020-09-27 |
Cole Poirier | icache.py fix translation mistake |
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2020-09-27 |
Cesar Strauss | Convert yet another few tests to be able to use latest... |
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2020-09-27 |
Luke Kenneth Casso... | add Makefile for creating ls180.il |
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2020-09-27 |
Luke Kenneth Casso... | rename sys_clk_i to clk_24_i |
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2020-09-27 |
Luke Kenneth Casso... | add clock selection mechanism |
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2020-09-26 |
Luke Kenneth Casso... | DMI-to-JTAG needed to be "sync" to get ack/resp right |
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2020-09-26 |
Luke Kenneth Casso... | do not use simdec2 in test_pipe_caller |
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2020-09-26 |
Luke Kenneth Casso... | fix annoying alu test_pipe_caller bug, missing asmcode |
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2020-09-26 |
Luke Kenneth Casso... | add alternative PowerDecode2 to branch test_pipe_caller |
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2020-09-26 |
Cesar Strauss | Convert a few more tests to be able to use cxxsim |
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2020-09-26 |
Luke Kenneth Casso... | try svf test of DMI MSR |
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2020-09-26 |
Luke Kenneth Casso... | make check of LDSTMode.update conditional in PowerDecoder2 |
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2020-09-26 |
Luke Kenneth Casso... | add ls180io.py |
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2020-09-26 |
Luke Kenneth Casso... | add openocd script to fire off svf test |
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2020-09-26 |
Luke Kenneth Casso... | get openocd svf test running, replicating jtag test |
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2020-09-26 |
Luke Kenneth Casso... | put test into "server" mode for connecting with openocd |
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2020-09-26 |
Luke Kenneth Casso... | create client-server version of jtag debug unit test |
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2020-09-26 |
Luke Kenneth Casso... | create client-server version of jtag debug unit test |
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2020-09-26 |
Luke Kenneth Casso... | class-ify jtagremote |
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2020-09-26 |
Luke Kenneth Casso... | send/receive jtagremote protocol |
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2020-09-26 |
Luke Kenneth Casso... | basic client/server socket example |
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2020-09-26 |
Luke Kenneth Casso... | add openocd configs |
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2020-09-26 |
Luke Kenneth Casso... | reduce sdram pins to smaller address and only 1 cs_n |
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2020-09-26 |
Luke Kenneth Casso... | only enable pads connections for ls180 for now |
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2020-09-25 |
Cole Poirier | icache.py fix several subtle bugs that were lines that... |
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2020-09-25 |
Cole Poirier | wb_types.py add reset value of 0b11111111 for WBSelType... |
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2020-09-24 |
Cesar Strauss | Use nmutil simulator module to simplify choosing among... |
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2020-09-24 |
Luke Kenneth Casso... | do not have to use uart_litex gpio_litex names |
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2020-09-24 |
Luke Kenneth Casso... | add comments |
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2020-09-24 |
Luke Kenneth Casso... | enable GPIO pads through C4M JTAG |
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2020-09-24 |
Luke Kenneth Casso... | c4m iopad integration working |
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2020-09-24 |
Cole Poirier | icache.py add some missing lines from icache.vhdl,... |
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2020-09-24 |
Cole Poirier | mem_types.py wb_types.py add name constructor to all... |
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2020-09-24 |
Cole Poirier | icache.py fixed all errors that raised python exception... |
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2020-09-24 |
Cesar Strauss | Fix whitespace, remove unused imports |
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2020-09-24 |
Luke Kenneth Casso... | brackets round imports looks cleaner? |
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2020-09-24 |
Luke Kenneth Casso... | add jtag c4m pins which gives us a way to connect IO... |
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2020-09-24 |
Cesar Strauss | Use nmutil simulator module to simplify choosing among... |
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2020-09-23 |
Luke Kenneth Casso... | cs_n and cke in sdram need to match in length |
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2020-09-23 |
Luke Kenneth Casso... | change litex sdram pinouts to ASIC type |
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2020-09-23 |
Luke Kenneth Casso... | redo litex SDCard to send out data/cmd o/i/en pins |
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2020-09-23 |
Luke Kenneth Casso... | sort out GPIO with i/o/oe in ls180 |
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2020-09-23 |
Luke Kenneth Casso... | add ls180 pinmap text file |
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2020-09-23 |
Luke Kenneth Casso... | attempt GPIO bi-directional |
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2020-09-23 |
Luke Kenneth Casso... | add I2C master to ls180 |
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2020-09-22 |
Luke Kenneth Casso... | add 2 PWMs (quick, easy to do) |
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2020-09-22 |
Luke Kenneth Casso... | move dmi_sim to separate module |
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2020-09-22 |
Jacob Lifshay | Revert "disable pia in div tests" |
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2020-09-22 |
Luke Kenneth Casso... | add openocd.cfg experiment |
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2020-09-22 |
Luke Kenneth Casso... | create a JTAG platform and connect it up. jtagremote... |
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2020-09-22 |
Luke Kenneth Casso... | add jtagremote to litex sim, add new "variant" to core... |
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2020-09-22 |
Luke Kenneth Casso... | link litex ls180soc JTAG pads |
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2020-09-22 |
Luke Kenneth Casso... | add jtag wishbone and jtag ports to libresoc litex... |
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2020-09-22 |
Luke Kenneth Casso... | add jtag interface to issuer_verilog |
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2020-09-22 |
Luke Kenneth Casso... | add sys_rst to Clock Reset Generator |
tree | commitdiff |
2020-09-22 |
Luke Kenneth Casso... | add JTAG IOpads and rename rst to sys_rst |
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2020-09-22 |
Luke Kenneth Casso... | add similar platforms to ls180.py |
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2020-09-22 |
Luke Kenneth Casso... | add JTAG bus module |
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2020-09-22 |
Luke Kenneth Casso... | split out dmi2jtag into own unit test |
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2020-09-22 |
Cesar Strauss | Port soc.experiment.alu_fsm to the new way of invoking... |
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2020-09-22 |
Luke Kenneth Casso... | disable pia in div tests |
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2020-09-22 |
Luke Kenneth Casso... | add MMU (commented out) |
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2020-09-21 |
Luke Kenneth Casso... | add missing file |
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2020-09-21 |
Luke Kenneth Casso... | add quick wishbone jtag test |
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2020-09-21 |
Luke Kenneth Casso... | experiment set dmi msr read |
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2020-09-21 |
Luke Kenneth Casso... | add DMI JTAG test |
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2020-09-21 |
Luke Kenneth Casso... | add JTAG basic unit test |
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2020-09-21 |
Luke Kenneth Casso... | arg complete rewrite of JTAG2DMI, based it on staf... |
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2020-09-20 |
Cesar Strauss | Add induction proof for the FSM Shifter |
tree | commitdiff |
2020-09-20 |
Cesar Strauss | Add bounded proof to FSM Shifter |
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2020-09-20 |
Cesar Strauss | Let the formal engine create some test cases for the... |
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2020-09-20 |
Luke Kenneth Casso... | resolve issues in async sim: must not drive async clock... |
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2020-09-20 |
Luke Kenneth Casso... | still experimenting with async FF sync |
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2020-09-20 |
Luke Kenneth Casso... | continuing async clock experimenting |
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2020-09-20 |
Luke Kenneth Casso... | add an async clock synchronizer experiment |
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2020-09-20 |
Luke Kenneth Casso... | first version code-morph on dmi2jtag |
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2020-09-19 |
Luke Kenneth Casso... | add pc_o not connected |
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2020-09-19 |
Luke Kenneth Casso... | set ROM to empty, set SRAM to tiny 0x200, get things... |
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2020-09-19 |
Cesar Strauss | Remove demonstration code |
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2020-09-19 |
Luke Kenneth Casso... | urk. wishbone slave devices declared incorrectly (I... semi_working_ecp5 |
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2020-09-19 |
Luke Kenneth Casso... | disable internal RAM set SRAM to much smaller |
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2020-09-19 |
Luke Kenneth Casso... | shrink size of SRAM to 8k, move things around |
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2020-09-19 |
Luke Kenneth Casso... | add (disabled) tri-state GPIO |
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2020-09-19 |
Luke Kenneth Casso... | remove the gpio peripheral which was previously hard... |
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2020-09-19 |
Luke Kenneth Casso... | add 3x EINTs to ls180soc |
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