2020-08-30 |
Cole Poirier | icache.py commit progress, about a third through the... |
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2020-08-29 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-29 |
Cole Poirier | mmu.py, dcache.py, mem_types.py change types capitaliza... |
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2020-08-29 |
Cole Poirier | mem_types add more types from common.vhdl specifially... |
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2020-08-29 |
Cole Poirier | mem_types.py arrange in alphabetical order for ease... |
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2020-08-29 |
Samuel A. Falvo II | BROKEN: xer_ov_o != dut.o.xer_ov.data ???!!! |
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2020-08-29 |
Cole Poirier | mmu.py remove duplicate comment left over from mmu... |
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2020-08-29 |
Cole Poirier | icache.py initial commit of first attempt at translatio... |
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2020-08-29 |
Cesar Strauss | Move new write_gtkw and its example to nmutil |
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2020-08-29 |
Luke Kenneth Casso... | minor code-shuffle, comments |
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2020-08-29 |
Luke Kenneth Casso... | slowly morphing towards using an XER bit-field selector... |
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2020-08-29 |
Samuel A. Falvo II | MUL pipeline formal proofs complete, I *think*. |
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2020-08-29 |
Luke Kenneth Casso... | break down XER into flags |
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2020-08-29 |
Luke Kenneth Casso... | add XER read via DMI interface to sim.py |
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2020-08-29 |
Luke Kenneth Casso... | add hack to get at XER through DMI interface |
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2020-08-29 |
Samuel A. Falvo II | WIP: prep for 64-bit insns |
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2020-08-29 |
Luke Kenneth Casso... | yep disable OE for MULH64/32 and EXTS and CNTZ |
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2020-08-29 |
Luke Kenneth Casso... | investigating CR mtocrf / mfocrf |
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2020-08-29 |
Luke Kenneth Casso... | add additional CR regression tests |
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2020-08-29 |
Luke Kenneth Casso... | allow pseudocode numbering to decrement in for-loops |
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2020-08-29 |
Luke Kenneth Casso... | add wat to write out raw binary assembled programs |
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2020-08-29 |
Luke Kenneth Casso... | CR FXM becomes a full mask. |
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2020-08-28 |
Cole Poirier | dcache.py add first attempt at translation of dcache_tb... |
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2020-08-27 |
Cole Poirier | dcache.py add skeleton sim and test adapted from mmu... |
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2020-08-27 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-27 |
Cole Poirier | dcache.py implement the remaining vhdl generate stateme... |
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2020-08-27 |
Luke Kenneth Casso... | https://bugs.libre-soc.org/show_bug.cgi?id=476 |
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2020-08-27 |
Luke Kenneth Casso... | xer so is not being passed through to CR0 |
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2020-08-27 |
Luke Kenneth Casso... | really bad hack to fix simulator bug in carry handling |
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2020-08-27 |
Luke Kenneth Casso... | augment addme test case to show bug #476 |
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2020-08-27 |
Luke Kenneth Casso... | add addze and addme uni tests |
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2020-08-27 |
Luke Kenneth Casso... | incompatibility with POWER9 on mulhw/u due to lack... |
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2020-08-27 |
Luke Kenneth Casso... | overflow-enable does not occur on shift operations |
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2020-08-27 |
Luke Kenneth Casso... | oink, write_cr shiftrot record width was zero (??) |
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2020-08-27 |
Luke Kenneth Casso... | sorting out shift_rot to use new output stage data... |
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2020-08-27 |
Luke Kenneth Casso... | need to read SO if Rc=1 |
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2020-08-27 |
Luke Kenneth Casso... | reorg of SO handling related to CR0 |
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2020-08-26 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-26 |
Cole Poirier | dcache.py replace subtypes/types/constant aliases with... |
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2020-08-26 |
Luke Kenneth Casso... | use sub-test in logical test_pipe_caller |
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2020-08-26 |
Luke Kenneth Casso... | investigating div fsm and simulator bug |
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2020-08-25 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-25 |
Cole Poirier | dcache.py rearrange, transform classes into functions... |
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2020-08-25 |
Jacob Lifshay | fix broken remainder for div FSM |
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2020-08-25 |
Jacob Lifshay | clean up formatting |
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2020-08-25 |
Luke Kenneth Casso... | although shift-rot does not alter XER.so it still needs... |
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2020-08-25 |
Luke Kenneth Casso... | add way to capture CR from DMI in litex sim |
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2020-08-25 |
Luke Kenneth Casso... | add CR read to DMI interface |
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2020-08-25 |
Luke Kenneth Casso... | shorten using temp vars |
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2020-08-25 |
Luke Kenneth Casso... | add CR DMI interface |
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2020-08-25 |
Luke Kenneth Casso... | add crxor unit test to qemu |
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2020-08-25 |
Cole Poirier | dcache.py fix whitespace, fomatting, syntax |
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2020-08-25 |
Cole Poirier | dcache.py fix formatting |
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2020-08-25 |
Cole Poirier | dcache.py move Reservation RecordObject to top of file |
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2020-08-25 |
Cole Poirier | dcache.py move RegStage1 RecordObject to top of file |
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2020-08-25 |
Cole Poirier | dcache.py move MemAccessRequest RecordObject to top... |
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2020-08-25 |
Cole Poirier | dcache.py move Stage0 RecordObject to top of file |
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2020-08-24 |
Luke Kenneth Casso... | argh, reading regfile over DMI was overlapped and corru... |
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2020-08-24 |
Luke Kenneth Casso... | add isel CR tests to run on qemu (confirmed working) |
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2020-08-24 |
Tobias Platen | TestCachedMemoryPortInterface cleanup |
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2020-08-24 |
Luke Kenneth Casso... | make it easier to select FSM/Pipe DIV unit |
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2020-08-24 |
Luke Kenneth Casso... | fix *another* ld-update-related timing / FSM issue |
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2020-08-24 |
Luke Kenneth Casso... | tidyup / shuffle after review |
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2020-08-24 |
Luke Kenneth Casso... | remove default parameter |
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2020-08-24 |
Luke Kenneth Casso... | "WAY" does not exist - range(NUM_WAYS) was intended |
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2020-08-24 |
Luke Kenneth Casso... | use WAY_BITS in appropriate locations |
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2020-08-24 |
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc |
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2020-08-24 |
Cole Poirier | dcache.py commit first full tranlation pass, about... |
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2020-08-23 |
Luke Kenneth Casso... | update copyright notices to include additional primary... |
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2020-08-23 |
Luke Kenneth Casso... | add load algebraic immediate unit test |
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2020-08-23 |
Luke Kenneth Casso... | add algebraic ld tests lwax, lwaux |
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2020-08-23 |
Michael Nolan | Add copyright to files I primarily authored in simulator/ |
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2020-08-23 |
Michael Nolan | Add copyright to files in fu/ that I was the primary... |
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2020-08-23 |
Michael Nolan | Add copyright statement to power_decoder.py |
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2020-08-23 |
Luke Kenneth Casso... | bring "core stopped" signal out through DMI interface |
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2020-08-23 |
Luke Kenneth Casso... | add in DMI "stat" loop which monitors core "stopping" |
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2020-08-23 |
Cesar Strauss | Allow an empty style, and passing default styles as... |
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2020-08-23 |
Cesar Strauss | Add comment node type |
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2020-08-23 |
Cesar Strauss | Add base and display styles |
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2020-08-23 |
Cesar Strauss | Apply style from node own name |
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2020-08-23 |
Cesar Strauss | Add color style |
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2020-08-23 |
Cesar Strauss | Collect styles from the tuple |
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2020-08-23 |
Cesar Strauss | Propagate the root style to all signals |
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2020-08-23 |
Luke Kenneth Casso... | comment why litex sim mem map is altered |
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2020-08-23 |
Luke Kenneth Casso... | multiply does not have invert_in, zero_a or invert_out |
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2020-08-22 |
Luke Kenneth Casso... | rename invert_a to invert_in because logical inverts RB |
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2020-08-22 |
Luke Kenneth Casso... | load bios not 1.bin unit test |
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2020-08-22 |
Luke Kenneth Casso... | add extra div regression tests |
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2020-08-22 |
Cesar Strauss | Move comments to the docstring |
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2020-08-22 |
Cesar Strauss | Walk the DOM and emit the trace names |
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2020-08-22 |
Luke Kenneth Casso... | add eqv to logical unit test |
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2020-08-22 |
Luke Kenneth Casso... | add nor and nand to unit test |
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2020-08-22 |
Luke Kenneth Casso... | moved to div pipe temporarily in compunits |
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2020-08-22 |
Luke Kenneth Casso... | bug in andc and orc, complement was taking place on... |
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2020-08-22 |
Luke Kenneth Casso... | extend addis test |
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2020-08-22 |
Luke Kenneth Casso... | add andc and orc tests, failing because RB needs invers... |
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2020-08-22 |
Luke Kenneth Casso... | modsd bug, https://bugs.libre-soc.org/show_bug.cgi... |
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2020-08-22 |
Cesar Strauss | First draft of a mini-language to describe GTKWave... |
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2020-08-22 |
Luke Kenneth Casso... | add regression test for nonzero addis |
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2020-08-22 |
Luke Kenneth Casso... | add means to run microwatt test binaries |
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