2019-02-06 |
Andrea Mondelli | sim: added missed macro definition on MacOS |
tree | commitdiff |
2019-02-05 |
Andrea Mondelli | misc: added missing override specifier |
tree | commitdiff |
2019-02-05 |
Javier Bueno | cpu: Made the Loop Predictor a SimObject |
tree | commitdiff |
2019-02-05 |
Jairo Balart | cpu: Made TAGE a SimObject that can be used by other... |
tree | commitdiff |
2019-02-05 |
Austin Harris | riscv: Get rid of ISA specific register types in Interr... |
tree | commitdiff |
2019-02-01 |
Javier Bueno | mem-cache: Updated version of the Signature Path Prefetcher |
tree | commitdiff |
2019-02-01 |
Anouk Van Laer | dev, arm: Removed contextId variable |
tree | commitdiff |
2019-02-01 |
Gabe Black | cpu, arch: Replace the CCReg type with RegVal. |
tree | commitdiff |
2019-01-31 |
Andreas Sandberg | python: Remove getCode() type workaround |
tree | commitdiff |
2019-01-31 |
Andreas Sandberg | sim: Prepare C++ side for Python 3 |
tree | commitdiff |
2019-01-31 |
Gabe Black | power: Get rid of some ISA specific register types. |
tree | commitdiff |
2019-01-31 |
Gabe Black | null: Get rid of some register type definitions. |
tree | commitdiff |
2019-01-31 |
Gabe Black | mips: Stop using architecture specific register types. |
tree | commitdiff |
2019-01-31 |
Gabe Black | alpha: Stop using architecture specific register types. |
tree | commitdiff |
2019-01-31 |
Gabe Black | x86: Stop using/defining some ISA specific register... |
tree | commitdiff |
2019-01-31 |
Gabe Black | riscv: Get rid of some ISA specific register types. |
tree | commitdiff |
2019-01-31 |
Gabe Black | arch: cpu: Rename *FloatRegBits* to *FloatReg*. |
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2019-01-30 |
Giacomo Gabrielli | arch,cpu: Add vector predicate registers |
tree | commitdiff |
2019-01-30 |
Giacomo Travaglini | arch-arm, configs: Create single instance of DTB autoge... |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch-arm: Remove floatReg operand type |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch-arm: Use VecElem instead of FloatReg for FP instru... |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch: Fix VecElem Operand generation in ISA parser |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | cpu, arch, arch-arm: Wire unused VecElem code in the... |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | cpu: O3 rename using the flatIndex instead of index |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch-arm: Inital vector rename mode depending on A32/A64 |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | cpu: Fix VecElemClass bugs in cpu models |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | cpu: Add VecElem entries in MinorCPU Scoreboard |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch-arm: Remove unused float operands |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch: Provide traceback when parsing ISA code |
tree | commitdiff |
2019-01-25 |
Nicholas Lindsay | python: Always throw TypeError on slave-slave connections |
tree | commitdiff |
2019-01-24 |
Gabe Black | hsail: Remove the MiscReg type. |
tree | commitdiff |
2019-01-24 |
Gabe Black | base: arch: Get rid of the now unused FloatRegVal type. |
tree | commitdiff |
2019-01-24 |
Ciro Santilli | dev-arm: fix --generate-dtb for ARM |
tree | commitdiff |
2019-01-24 |
Rekai Gonzalez-Alb... | cpu-o3: O3 LSQ Generalisation |
tree | commitdiff |
2019-01-23 |
Giacomo Travaglini | arch-arm: Implement LoadAcquire/StoreRelease in AArch32 |
tree | commitdiff |
2019-01-23 |
Giacomo Travaglini | arch-arm: IsStoreConditional flag set depending on... |
tree | commitdiff |
2019-01-23 |
Giacomo Travaglini | arch-arm: Remove SWP and SWPB instructions |
tree | commitdiff |
2019-01-23 |
Gabe Black | systemc: Fix TLM related includes. |
tree | commitdiff |
2019-01-23 |
Gabe Black | arm: Replace MiscReg with RegVal in utility.(hh|cc). |
tree | commitdiff |
2019-01-23 |
Zicong Wang | mem-ruby: Fix missing TBE allocation and deallocation |
tree | commitdiff |
2019-01-22 |
Gabe Black | sparc: Get rid of some register type definitions. |
tree | commitdiff |
2019-01-22 |
Gabe Black | arch: cpu: Stop passing around misc registers by reference. |
tree | commitdiff |
2019-01-22 |
Gabe Black | arm: Get rid of some register type definitions. |
tree | commitdiff |
2019-01-22 |
Gabe Black | arm: dev: Replace ArmISA::MiscReg with RegVal in the... |
tree | commitdiff |
2019-01-22 |
Ciro Santilli | arch-arm: implement the GDB XML target description... |
tree | commitdiff |
2019-01-22 |
Ciro Santilli | scons: add helpers to access GDB XML description files |
tree | commitdiff |
2019-01-22 |
Ciro Santilli | scons: allow embedding arbitrary blobs into the gem5... |
tree | commitdiff |
2019-01-22 |
Ciro Santilli | base: add support for GDB's XML architecture definition |
tree | commitdiff |
2019-01-22 |
Giacomo Travaglini | arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers |
tree | commitdiff |
2019-01-22 |
Sascha Bischoff | mem: Add tryTiming suppport to CommMonitor |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se add readv and modifies writev |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se: add ability to get/set sock metadata |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se: add syscalls related to polling |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se: add calls for network transmissions |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se: add socket-based functionality |
tree | commitdiff |
2019-01-18 |
Daniel R. Carvalho | base: Fix unitialized storage |
tree | commitdiff |
2019-01-17 |
Nikos Nikoleris | mem: Allow inserts in the begining of a packet queue |
tree | commitdiff |
2019-01-17 |
Nikos Nikoleris | mem: Determine if a packet queue forces ordering at... |
tree | commitdiff |
2019-01-17 |
Nikos Nikoleris | cpu-o3: Make the smtCommitPolicy a Param.ScopedEnum |
tree | commitdiff |
2019-01-17 |
Nikos Nikoleris | cpu-o3: Make the smtROBPolicy a Param.ScopedEnum |
tree | commitdiff |
2019-01-17 |
Nikos Nikoleris | cpu-o3: Make the smtIQPolicy a Param.ScopedEnum |
tree | commitdiff |
2019-01-17 |
Nikos Nikoleris | cpu-o3: Make the smtLSQPolicy a Param.ScopedEnum |
tree | commitdiff |
2019-01-17 |
Nikos Nikoleris | cpu-o3: Make the smtFetchPolicy a Param.ScopedEnum |
tree | commitdiff |
2019-01-17 |
Nikos Nikoleris | python: Add support for scoped enums |
tree | commitdiff |
2019-01-16 |
Gabe Black | cpu: dev: sim: gpu-compute: Banish some ISA specific... |
tree | commitdiff |
2019-01-16 |
Gabe Black | arch: Make the ISA register types aliases for the globa... |
tree | commitdiff |
2019-01-16 |
Gabe Black | arm: Make the fp register types 64 bits. |
tree | commitdiff |
2019-01-16 |
Javier Bueno | mem-cache: Access Map Pattern Matching Prefetcher |
tree | commitdiff |
2019-01-16 |
Javier Bueno | mem-cache: Signature Path Prefetcher |
tree | commitdiff |
2019-01-16 |
Javier Bueno | mem-cache: allow prefetchers to emit page crossing... |
tree | commitdiff |
2019-01-16 |
Javier Bueno | mem-cache: virtual address support for prefetchers |
tree | commitdiff |
2019-01-16 |
Giacomo Travaglini | arch-arm: Read VMPIDR instead of MPIDR when EL2 is... |
tree | commitdiff |
2019-01-16 |
Anouk Van Laer | arch-arm: Added TLBI_ALL EL2 instruction |
tree | commitdiff |
2019-01-16 |
Alec Roelke | arch-riscv: Add interrupt handling |
tree | commitdiff |
2019-01-16 |
Alec Roelke | arch-riscv: Fix reset function and style |
tree | commitdiff |
2019-01-15 |
Giacomo Travaglini | cpu: Fix usage of setArchVecElem |
tree | commitdiff |
2019-01-15 |
Giacomo Travaglini | arch-arm: Fix usage of RegId constructor for VecElem |
tree | commitdiff |
2019-01-14 |
Gabe Black | arm: Stop using the FloatReg and FloatRegBits types. |
tree | commitdiff |
2019-01-14 |
Gabe Black | config: De-nest the code in Port.splice(). |
tree | commitdiff |
2019-01-14 |
Gabe Black | config: Fix an error message in Port.splice(). |
tree | commitdiff |
2019-01-11 |
Andrea Mondelli | misc: updated shabang for python script |
tree | commitdiff |
2019-01-10 |
Javier Setoain | sim-se, arch-arm: Add support for getdents64 |
tree | commitdiff |
2019-01-10 |
Andreas Sandberg | arch-arm, sim-se: Add support for TLS in clone |
tree | commitdiff |
2019-01-10 |
Andreas Sandberg | arch-arm, sim-se: Fix incorrect SP handling in clone |
tree | commitdiff |
2019-01-10 |
Andreas Sandberg | sim-se: Refactor clone to avoid most ifdefs |
tree | commitdiff |
2019-01-10 |
Andreas Sandberg | sim-se: Correctly calculate next PC in clone |
tree | commitdiff |
2019-01-10 |
Andreas Sandberg | sim-se: Use CONFIG_CLONE_BACKWARDS for Arm |
tree | commitdiff |
2019-01-10 |
Javier Setoain | arch-arm, sim-se: Wire up syscalls needed for pthreads |
tree | commitdiff |
2019-01-10 |
Jairo Balart | dev-arm: Add a VExpress_GEM5_V2 platform with GICv3... |
tree | commitdiff |
2019-01-10 |
Jairo Balart | dev-arm: Add a GICv3 model |
tree | commitdiff |
2019-01-10 |
Giacomo Travaglini | base: Make it possible to convert strings to enums |
tree | commitdiff |
2019-01-10 |
Gabe Black | systemc: Fix a function which was broken during style... |
tree | commitdiff |
2019-01-09 |
Ivan Pizarro | arch-arm: Additional bits in misc ARM registers to... |
tree | commitdiff |
2019-01-09 |
Gabe Black | systemc: Make input.txt a dependency for the tlm/endian... |
tree | commitdiff |
2019-01-09 |
Gabe Black | systemc: Exclude some failing systemc TLM tests in... |
tree | commitdiff |
2019-01-09 |
Gabe Black | systemc: Remove the TLM dependence on a non-standard... |
tree | commitdiff |
2019-01-09 |
Gabe Black | systemc: Stop using the sc_string_view type. |
tree | commitdiff |
2019-01-09 |
Gabe Black | systemc: Replace sc_core::sc_type_index with std::type_... |
tree | commitdiff |
2019-01-09 |
Gabe Black | systemc: Stop using the Accellera specific "none" globa... |
tree | commitdiff |
2019-01-09 |
Gabe Black | systemc: Rename tlm_core header files to have a .hh... |
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