o3 cpu: Remove unused variables
[gem5.git] / src /
2012-10-15 Nilay Vaish ruby: register multiple memory controllers
2012-10-15 Nilay Vaishruby: remove AbstractMemOrCache
2012-10-15 Nilay Vaishruby: allow function definition in slicc structs
2012-10-15 Nilay Vaishruby banked array: do away with event scheduling
2012-10-15 Nilay Vaishruby: reset timing after cache warm up
2012-10-15 Andreas HanssonMem: Fix incorrect logic in bus blocksize check
2012-10-15 Andreas HanssonPort: Add protocol-agnostic ports in the port hierarchy
2012-10-15 Andreas HanssonMem: Separate the host and guest views of memory backin...
2012-10-15 Andreas HanssonCheckpoint: Make system serialize call children
2012-10-15 Andreas HanssonMem: Use deque instead of list for bus retries
2012-10-15 Andreas HanssonFix: Address a few minor issues identified by cppcheck
2012-10-15 Andreas HanssonMem: Use cycles to express cache-related latencies
2012-10-15 Andreas HanssonRegression: Use CPU clock and 32-byte width for L1...
2012-10-15 Andreas HanssonClock: Inherit the clock from parent by default
2012-10-15 Andreas HanssonParam: Fix proxy traversal to support chained proxies
2012-10-15 Andreas HanssonMem: Use range operations in bus in preparation for...
2012-10-11 Andreas HanssonMem: Determine bus block size during initialisation
2012-10-11 Andreas HanssonDoxygen: Update the version of the Doxyfile
2012-10-02 Nilay Vaishruby: makes some members non-static
2012-10-02 Nilay Vaishruby: changes to simple network
2012-10-02 Nilay Vaishruby: rename template_hack to template
2012-10-02 Nilay Vaishruby: remove unused code in protocols
2012-10-02 Nilay Vaishruby: remove some unused things in slicc
2012-10-02 Nilay Vaishruby: move functional access to ruby system
2012-09-30 Nilay VaishMI coherence protocol: add copyright notice
2012-09-25 Djordje KovacevicMEM: Put memory system document into doxygen
2012-09-25 Mrinmoy GhoshCache: add a response latency to the caches
2012-09-25 Sascha BischoffStatistics: Add a function to configure periodic stats...
2012-09-25 Dam SunwooARM: added support for flattened device tree blobs
2012-09-25 Ali SaidiO3: Pack the comm structures a bit better to reduce...
2012-09-25 Ali Saidimem: Add a gasket that allows memory ranges to be re...
2012-09-25 Ali SaidiARM: Squash outstanding walks when instructions are...
2012-09-25 Andreas Sandbergarm: Use a static_assert to test that miscRegName[...
2012-09-25 Andreas Sandbergbase: Check for static_assert support and provide fallback
2012-09-25 Andreas Sandbergsim: Move CPU-specific methods from SimObject to the...
2012-09-25 Andreas Sandbergsim: Remove SimObject::setMemoryMode
2012-09-25 Djordje KovacevicCPU: Add abandoned instructions to O3 Pipe Viewer
2012-09-25 Nathanael PremillieuARM: Inst writing to cntrlReg registers not set as...
2012-09-25 Ali SaidiARM: Predict target of more instructions that modify PC.
2012-09-25 Andreas Sandbergbuild: Add missing dependencies when building param...
2012-09-23 Joel HestnessRubyPort and Sequencer: Fix draining
2012-09-21 Andreas HanssonDRAM: Introduce SimpleDRAM to capture a high-level...
2012-09-21 Andreas HanssonTrafficGen: Add a basic traffic generator
2012-09-21 Andreas HanssonMem: Tidy up bus member variables types
2012-09-21 Lluc AlvarezSE: Ignore FUTEX_PRIVATE_FLAG of sys_futex
2012-09-20 Anthony Gutierrezbus: removed outdated warn regarding 64 B block sizes
2012-09-19 Andreas HanssonMem: Remove the file parameter from AbstractMemory
2012-09-19 Andreas HanssonAddrRange: Transition from Range<T> to AddrRange
2012-09-19 Andreas HanssonAddrRange: Simplify Range by removing stream input...
2012-09-19 Andreas HanssonAddrRange: Remove unused range_multimap
2012-09-19 Andreas HanssonAddrRange: Simplify AddrRange params Python hierarchy
2012-09-19 Nilay Vaishruby: eliminate typedef integer_t
2012-09-19 Nilay Vaishruby: avoid using g_system_ptr for event scheduling
2012-09-18 Andreas HanssonMem: Add a maximum bandwidth to SimpleMemory
2012-09-14 Andreas Hanssongcc: Enable Link-Time Optimization for gcc >= 4.6
2012-09-14 Andreas Hanssonscons: Add a target for google-perftools profiling
2012-09-14 Andreas Hanssonscons: Restructure ccflags and ldflags
2012-09-14 Andreas Hanssonscons: Use c++0x with gcc >= 4.4 instead of 4.6
2012-09-13 Joel HestnessStandard Switch: Drain the system before switching...
2012-09-13 Joel HestnessBase CPU: Initialize profileEvent to NULL
2012-09-12 Jason PowerRuby: Modify Scons so that we can put .sm files in...
2012-09-12 Anthony Gutierrezstats: remove duplicate instruction stats from the...
2012-09-11 Andreas Hanssonclang: Fix issues identified by the clang static analyzer
2012-09-11 Lena OlsonCache: Split invalidateBlk up to seperate block vs...
2012-09-11 Nilay VaishX86: make use of register predication
2012-09-11 Nilay Vaishx86: Add a separate register for D flag bit
2012-06-03 Nilay VaishISA Parser: Allow predication of source and destination...
2012-09-11 Nilay VaishRuby: Use uint32_t instead of uint32 everywhere
2012-09-11 Nilay VaishRuby: Use uint8_t instead of uint8 everywhere
2012-09-10 Nilay VaishRuby System: Convert to Clocked Object
2012-09-10 Nilay VaishRuby Slicc: remove the call to cin.get() function
2012-09-10 Marco ElverMem: Allow serializing of more than INT_MAX bytes
2012-09-10 Palle LyckegaardNetBSD: Build on NetBSD
2012-09-10 Andreas HanssonAddrRange: Remove the unused range_ops header
2012-09-10 Andreas HanssonInet: Remove the SackRange and its use
2012-09-10 Andreas HanssonDevice: Bump PIO and PCI latencies to more reasonable...
2012-09-07 Andreas Sandbergsim: Update the SimObject documentation
2012-09-07 Andreas Sandbergsim: Remove the unused SimObject::regFormulas method
2012-09-07 Ali SaidiO3: Get rid of incorrect assert in RAS.
2012-09-07 Ali Saididev: Fix bifield definition in timer_cpulocal.hh
2012-09-07 Ali SaidiIgbe: Newer kernels seem to allow TSO headers and packe...
2012-09-07 Krishnendra Nathellasim: add validation to make sure there is memory where...
2012-09-07 Ali Saidiloader: initialize all memory in the ObjectFile objects.
2012-09-07 Ali SaidiARM: Fix one of the timers used in the VExpress EMM...
2012-09-07 Andreas HanssonParam: Transition to Cycles for relevant parameters
2012-09-06 Joel HestnessRuby Memory Controller: Fix clocking
2012-08-28 Jason PowerRuby: Correct DataBlock =operator
2012-08-28 Andreas HanssonClock: Add a Cycles wrapper class and use where applicable
2012-08-28 Andreas HanssonClock: Rework clocks to avoid tick-to-cycle transformations
2012-08-28 Andreas HanssonPort: Stricter port bind/unbind semantics
2012-08-28 Andreas HanssonChecker: Fix checker CPU ports
2012-08-28 Andreas Hanssonswig: Disable unused value warning with llvm 3.1 compilers
2012-08-28 Anthony Gutierrezsim: fix overflow check in simulate because Tick is...
2012-08-27 Nilay VaishRuby: remove README.debugging and Decommissioning_note
2012-08-27 Nilay VaishSystem: Remove redundant call to startupCPU
2012-08-27 Nilay VaishRuby: Remove RubyEventQueue
2012-08-27 Nilay VaishRuby Memory Vector: Allow more than 4GB of memory
2012-08-25 Nilay VaishMESI Protocol: Correct the virtual network in profile...
2012-08-25 Nilay VaishMESI Coherence Protocol: Add copyright notice
2012-08-22 Andreas HanssonDMA: Refactor the DMA device and align timing and atomic
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