2021-12-05 |
Luke Kenneth Casso... | code-comments |
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2021-12-05 |
Luke Kenneth Casso... | whitespace and minor cleanup of D-Cache |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | more use of TLBHit Record in D-Cache |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | correct tlb_hit_way and index sizes, use TLBHit Record... |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | use TLBRecord in D-Cache for which TLB is selected |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | split out TLBRecord, correct number of valid bits |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | use Record in DCache for TLB |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | use Record in D-Cache Cache Tags |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | whitespace |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | use Record for I-Cache Cache Tag/Valid |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | whitespace |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | use Record for ICache TLB |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | sorting out test_mmu_dcache.py to use wb_get |
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2021-12-05 |
Luke Kenneth Casso... | convert icache.py to standard wishbone Interface |
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2021-12-05 |
Luke Kenneth Casso... | fake up wishbone stall signal in icache. |
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2021-12-05 |
Luke Kenneth Casso... | fix icache row store issue |
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2021-12-05 |
Luke Kenneth Casso... | using same tag/row functions as in dcache.py |
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2021-12-05 |
Luke Kenneth Casso... | more signal sizes in icache.py |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | incorrect Signal sizes in icache.py, |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | sorting out icache.py, used to work |
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2021-12-05 |
Luke Kenneth Casso... | remove redundant code |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | add I-Cache standard bus (not used yet) |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | remove yet another duplicate copy of wb_get, possible... |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | replace yet another duplicate copy of wb_get, possible... |
tree | commitdiff |
2021-12-05 |
Luke Kenneth Casso... | wishbone bus convert on dcache |
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2021-12-05 |
Luke Kenneth Casso... | correct import of wg_get function |
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2021-12-04 |
Luke Kenneth Casso... | remove yet another duplicated copy of wb_get and add... |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | rename function which needs replacing |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | should have been using common version of wb_get, not... |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | should not have been duplicating wb_get function in... |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | get test_mmu_dcache.py working again |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | remove wb_get, should not have been duplicated |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | remove wb_get, should not have been massively duplicate... |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | fix return results from pi_ld |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | wark-wark, broke mmu with removing rin. reverted |
tree | commitdiff |
2021-12-04 |
Tobias Platen | fixed wait_addr to exit immediately on exception |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | tidyup, comments |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | tidyup mmu |
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2021-12-04 |
Luke Kenneth Casso... | sigh in MMU FSM use direct access to ldst.dar/dsisr... |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | remove DAR from PortInterface (where is the data going... |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | stop using dar_o from PortInterface, get DAR directly... |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | put DSISR and DAR publicly accessible in LoadStore1 |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | whoops fix up exception happened if alignment triggers... |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | fix pi_st which should not be trying to wait for the... |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | fixing DAR updating from exceptions |
tree | commitdiff |
2021-12-04 |
Luke Kenneth Casso... | whoops |
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2021-12-04 |
Luke Kenneth Casso... | MMU lookup DSISR load bit inverted in LoadStore1 |
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2021-12-04 |
Luke Kenneth Casso... | store DAR in LoadStore1 |
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2021-12-04 |
Luke Kenneth Casso... | not busy if excrption occurs on MMU_LOOKUP in loadstore.py |
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2021-12-04 |
Luke Kenneth Casso... | add means to update dsisr from MMU FSM. TODO: add a... |
tree | commitdiff |
2021-12-03 |
Luke Kenneth Casso... | priv_mode/virt_mode are set in the request, which is... |
tree | commitdiff |
2021-12-03 |
Luke Kenneth Casso... | in loadstore.py set align_intr from request which comes... |
tree | commitdiff |
2021-12-03 |
Luke Kenneth Casso... | driver conflict on priv_mode and virt_mode, do not... |
tree | commitdiff |
2021-12-03 |
Luke Kenneth Casso... | fix up test_loadstore1.py |
tree | commitdiff |
2021-12-03 |
Luke Kenneth Casso... | in loadstore.py, when an exception is done or if the FSM |
tree | commitdiff |
2021-12-03 |
Luke Kenneth Casso... | fix PortInterfaceBase |
tree | commitdiff |
2021-12-03 |
Luke Kenneth Casso... | fix up LDST test functions pi_ld and pi_st to respect... |
tree | commitdiff |
2021-12-03 |
Luke Kenneth Casso... | whitespace |
tree | commitdiff |
2021-12-03 |
Luke Kenneth Casso... | add misaligned ld/st to trigger an exception |
tree | commitdiff |
2021-12-03 |
Luke Kenneth Casso... | comment out dsisr and dar in mmu FSM for now |
tree | commitdiff |
2021-12-02 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-12-02 |
Tobias Platen | cleanup test_compldst_multi_mmu.py |
tree | commitdiff |
2021-12-02 |
Luke Kenneth Casso... | add a bitvector remap function, the plan is to use... |
tree | commitdiff |
2021-12-02 |
Tobias Platen | fix test_random in test_loadstore1 |
tree | commitdiff |
2021-12-02 |
Luke Kenneth Casso... | use new namedtuple in core when calling regspec_decode() |
tree | commitdiff |
2021-12-02 |
Luke Kenneth Casso... | add module parameter to regspec_decode and therefore... |
tree | commitdiff |
2021-12-02 |
Jacob Lifshay | remove bitmanip fu cuz ternlogi (the only instruction... |
tree | commitdiff |
2021-12-02 |
Jacob Lifshay | add ternlogi to shiftrot |
tree | commitdiff |
2021-12-02 |
Jacob Lifshay | format code |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | stack of changes to MultiCompUnit to speed it up |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | experimenting with option to shorten MultiCompUnit... |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | create single-stage ALU pipeline, shorten latency on... |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | allow MultiCompUnit to set read and write latches to... |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | FunctionUnitBaseMulti which derives from ReservationSta... |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | better name for read latch in core.py |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | use m.submodules[name] instead of getattr |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | remove redundant / mis-named variable in core |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | code-comments |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | remove unneeded data structure in core |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | whoops treereduce on write-vector set/clr error |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | more code-cleanup |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | use new regspec_decode and fu.get_iospec functions |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | core tidyup |
tree | commitdiff |
2021-12-01 |
Luke Kenneth Casso... | add Regspecs get_io_spec function |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | start allocating more FUs (more ReservationStations) |
tree | commitdiff |
2021-11-30 |
Tobias Platen | random loadstore1 test: readback written data |
tree | commitdiff |
2021-11-30 |
Tobias Platen | reenable dcbz test case |
tree | commitdiff |
2021-11-30 |
Tobias Platen | return correct data from microwatt |
tree | commitdiff |
2021-11-30 |
Tobias Platen | cleanup test_loadstore1.py |
tree | commitdiff |
2021-11-30 |
Tobias Platen | loadstore: add done_delay |
tree | commitdiff |
2021-11-30 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | add LogicalTestCases back in to test_core.py (pass) |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | let PowerDecode2 decide which operand class to use... |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | use latched readflag (recspec_decode_read "ok") instead... |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | tidyup on read-flag latches |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | fix read-decode information by latching not just the... |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | fix write-after-write hazard checking |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | allow busy to settle before checking state in test_core.py |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | only check regs right at the end in test_core.py overla... |
tree | commitdiff |
2021-11-30 |
Luke Kenneth Casso... | move sim call before core run in test_core.py |
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