2020-07-02 |
Luke Kenneth Casso... | reduce DIV radix to 1 |
tree | commitdiff |
2020-07-02 |
Luke Kenneth Casso... | add DIV function unit to compunits |
tree | commitdiff |
2020-07-02 |
Luke Kenneth Casso... | add trap function unit into compunits |
tree | commitdiff |
2020-07-02 |
Luke Kenneth Casso... | add bare wishbone option to TestIssuer, sort out ports |
tree | commitdiff |
2020-07-02 |
Luke Kenneth Casso... | use single-arg pspec for TestIssuer and Core |
tree | commitdiff |
2020-07-02 |
Cesar Strauss | Present the ALU result only when valid_o is active |
tree | commitdiff |
2020-07-01 |
Luke Kenneth Casso... | whoops missed some cases in unit test changing ALUHelpers |
tree | commitdiff |
2020-07-01 |
Luke Kenneth Casso... | minor reorg on how Bus and Config classes are set up |
tree | commitdiff |
2020-07-01 |
Luke Kenneth Casso... | whoops swapped trap test instructions accidentally |
tree | commitdiff |
2020-07-01 |
Luke Kenneth Casso... | print out msr for debug |
tree | commitdiff |
2020-07-01 |
Luke Kenneth Casso... | attempting to add SPRs to rfid test |
tree | commitdiff |
2020-07-01 |
Luke Kenneth Casso... | add OP_SC |
tree | commitdiff |
2020-07-01 |
Luke Kenneth Casso... | trap test check results |
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2020-07-01 |
Luke Kenneth Casso... | add name "test_issuer" to ilang conversion |
tree | commitdiff |
2020-07-01 |
Luke Kenneth Casso... | add in trap compunit |
tree | commitdiff |
2020-07-01 |
Luke Kenneth Casso... | add rfid and td/tw trap test |
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2020-07-01 |
Luke Kenneth Casso... | continue debugging trap pipeline |
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2020-07-01 |
Luke Kenneth Casso... | debugging trap pipeline |
tree | commitdiff |
2020-07-01 |
Luke Kenneth Casso... | start running trap unit test, fixing errors |
tree | commitdiff |
2020-06-30 |
Luke Kenneth Casso... | add lte ltu for use by twi and other trap functions |
tree | commitdiff |
2020-06-30 |
Luke Kenneth Casso... | add in pseudocode keyword into mdwn isa files |
tree | commitdiff |
2020-06-30 |
Luke Kenneth Casso... | code-morph on div pipeline |
tree | commitdiff |
2020-06-29 |
Luke Kenneth Casso... | add README for fu directory |
tree | commitdiff |
2020-06-29 |
Luke Kenneth Casso... | use correct ALUHelpers in div test |
tree | commitdiff |
2020-06-29 |
Luke Kenneth Casso... | sort out syntax errors in div |
tree | commitdiff |
2020-06-29 |
Luke Kenneth Casso... | first unit test for div |
tree | commitdiff |
2020-06-29 |
Luke Kenneth Casso... | add ignore for parsetab.py |
tree | commitdiff |
2020-06-29 |
Luke Kenneth Casso... | add autogenerated do not commit comment |
tree | commitdiff |
2020-06-29 |
Luke Kenneth Casso... | separate out divide by zero cases |
tree | commitdiff |
2020-06-29 |
Luke Kenneth Casso... | update OV and OV32 ISACaller flags if overflow occurs |
tree | commitdiff |
2020-06-29 |
Luke Kenneth Casso... | attempting to add overflow setting in ISACaller |
tree | commitdiff |
2020-06-29 |
Luke Kenneth Casso... | whoops, hex parser digits are in multiples of 4 bits |
tree | commitdiff |
2020-06-29 |
Luke Kenneth Casso... | fetch instructions from bare wishbone fetch unit |
tree | commitdiff |
2020-06-28 |
Cesar Strauss | Start with a simpler test case |
tree | commitdiff |
2020-06-28 |
Cesar Strauss | Let p.ready_o be active while the test ALU is idle |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | add cached fetch unit pass-through args |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | need args to WishboneArbiter, match data width size |
tree | commitdiff |
2020-06-28 |
Cesar Strauss | Add missing ports to the test ALU |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | read from instruction memory using FetchUnitInterface |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | add Config Fetch interface and quick unit test |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | add test instruction memory |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | add readonly option to TestMemory |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | expand instruction bus width to 64 bit, start on a... |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | parameterise minerva i-cache |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | got Pi2LSUI FSM working |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | sram address do not cut by LSBs |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | new Pi2LSUI working, using PortInterfaceBase |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | start new version of Pi2LSUI based on PortInterfaceBase |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | pass addr/mask through to PortInterfaceBase rd/wr addr |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | cleanup (remove unneeded imports) |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | more code-shuffle for TestMemoryPortInterface |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | more code-shuffle for TestMemoryPortInterface |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | minor cleanup, put get/set rdport/wrport into function |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | merge LDSTPort into TestMemoryPortInterface |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | use PortInterface connect_port |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | use PortInterface connect_port |
tree | commitdiff |
2020-06-28 |
Luke Kenneth Casso... | attempt to get Pi2LSUI FSM working |
tree | commitdiff |
2020-06-27 |
Luke Kenneth Casso... | only activate ld_in_progress if addr is ok |
tree | commitdiff |
2020-06-27 |
Luke Kenneth Casso... | make Memory accessible via TestSRAMBareLoadStoreUnit |
tree | commitdiff |
2020-06-27 |
Luke Kenneth Casso... | increase (double) address width in TstL0CacheBuffer |
tree | commitdiff |
2020-06-27 |
Luke Kenneth Casso... | increase (double) address width in TstL0CacheBuffer |
tree | commitdiff |
2020-06-27 |
Luke Kenneth Casso... | unit test in l0_cache to connect to testpi and test_bare_wb |
tree | commitdiff |
2020-06-27 |
Luke Kenneth Casso... | make PortInterface modules consistent with same API |
tree | commitdiff |
2020-06-27 |
Luke Kenneth Casso... | use ConfigMemoryPortInterface in TstL0CacheBuffer |
tree | commitdiff |
2020-06-27 |
Luke Kenneth Casso... | fix TestMemLoadStoreUnit, it required a FSM to monitor... |
tree | commitdiff |
2020-06-27 |
Luke Kenneth Casso... | add wishbone Pi2LSUI test |
tree | commitdiff |
2020-06-27 |
Luke Kenneth Casso... | reconfigureable PortInterface testing now possible |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | name issue in Pi2LSUI |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | whitespace and imports |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | whitespace |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | slight reorg on test_pi2ls.py |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | correct address in pi2ls |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | oops forgot to initialise base class of TestMemLoadStor... |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | add in LenExpand shift/mask |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | add quick test showing Pi2LSUI not quite reading/writing to |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | remove extraneous yields |
tree | commitdiff |
2020-06-26 |
Michael Nolan | Modify pi2ls so it passes the portinterface unit tests |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | set address ok and fix unit test to check it properly |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | add pi.busy_o connection, increase to 64 bit |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | unit test broken is ok :) |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | set pi.ld.ok to 1 if pi.is_ld_i is set |
tree | commitdiff |
2020-06-26 |
Michael Nolan | Move tests for pimem to new file, add ability to test... |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | load/store unit test needed to wait for busy_o |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | whitespace |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | clean up output from BareLoadStoreUnit |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | halve the test memory size again |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | shrink test memory size down to only 64 words |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | investigating why write-enable not getting passed through |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | whoops forgot to call parent elaborate |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | add test of SRAM through wishbone bus |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | code-morph which redirects lsmem unit test through... |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | add a test SRAM that lives behind a minerva LoadStoreUn... |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | dynamically specify wishbone layout (no longer hardcode... |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | add reconfigureable Load/Store class |
tree | commitdiff |
2020-06-26 |
Luke Kenneth Casso... | extra parameterification of minerva LoadStoreUnits |
tree | commitdiff |
2020-06-25 |
Luke Kenneth Casso... | allow Pi2LSUI to accept incoming PortInterface and... |
tree | commitdiff |
2020-06-25 |
Luke Kenneth Casso... | add extra parameter, mask_wid, to TestMemLoadStoreUnit |
tree | commitdiff |
2020-06-25 |
Luke Kenneth Casso... | start connecting up Pi2LSUI |
tree | commitdiff |
2020-06-25 |
Luke Kenneth Casso... | add LenExpand module, tidyup on docstring |
tree | commitdiff |
2020-06-25 |
Luke Kenneth Casso... | add beginnings of Pi2LSUI |
tree | commitdiff |
next |