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Revert "Add INIT parameter to all ff/latch cells"
[yosys.git]
/
techlibs
/
common
/
simcells.v
2019-02-17
Eddie Hung
Revert "Add INIT parameter to all ff/latch cells"
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2019-02-17
Eddie Hung
Merge https://github.com/YosysHQ/yosys into dff_init
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2019-02-06
Eddie Hung
Add INIT parameter to all ff/latch cells
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2018-12-16
Clifford Wolf
Merge pull request #704 from webhat/feature/fix-awk
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2018-12-05
Clifford Wolf
Merge pull request #709 from smunaut/issue_708
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2018-12-05
Clifford Wolf
Merge pull request #718 from whitequark/gate2lut
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2018-12-05
whitequark
Fix typo.
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2017-05-17
Clifford Wolf
Add $_ANDNOT_ and $_ORNOT_ gates
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2016-10-14
Clifford Wolf
Added $global_clock verilog syntax support for creating...
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-02-01
Clifford Wolf
Progress in cell library documentation
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-10-20
Clifford Wolf
Progress on cell help messages
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2015-10-17
Clifford Wolf
Progress on cell help messages
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2015-10-14
Clifford Wolf
Added more cell descriptions
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2015-10-14
Clifford Wolf
Added first help messages for cell types
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2015-08-16
Clifford Wolf
Added $tribuf and $_TBUF_ sim models
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2015-08-14
Larry Doolittle
Another block of spelling fixes
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-04-05
Clifford Wolf
Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-12-08
Clifford Wolf
Added $_DFFE_??_ cell types
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2014-10-03
Clifford Wolf
Added $_BUF_ cell type
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-08-16
Clifford Wolf
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_...
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2014-08-15
Clifford Wolf
Renamed $_INV_ cell type to $_NOT_
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2014-07-31
Clifford Wolf
Renamed "stdcells.v" to "techmap.v"
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2014-03-31
Clifford Wolf
Added support for dlatchsr cells
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2013-11-24
Clifford Wolf
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
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