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Try new LUT delays
[yosys.git]
/
techlibs
/
common
/
simlib.v
2019-05-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-21
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-05-08
Clifford Wolf
Merge pull request #991 from kristofferkoch/gcc9-warnings
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2019-05-06
Clifford Wolf
Merge pull request #946 from YosysHQ/clifford/specify
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2019-05-06
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys into...
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2019-05-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into cliff...
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2019-04-23
Clifford Wolf
Improve $specrule interface
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2019-04-23
Clifford Wolf
Improve $specrule interface
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2019-04-23
Clifford Wolf
Add $specrule cells for $setup/$hold/$skew specify...
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2019-04-23
Clifford Wolf
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better...
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2019-04-23
Clifford Wolf
Add $specify2 and $specify3 cells to simlib
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2019-02-19
Eddie Hung
Merge branch 'master' into xaig
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2019-02-19
Eddie Hung
Merge branch 'master' into read_aiger
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2019-02-18
Eddie Hung
Merge branch 'dff_init' into read_aiger
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2019-02-17
Eddie Hung
Revert "Add INIT parameter to all ff/latch cells"
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2019-02-17
Eddie Hung
Merge https://github.com/YosysHQ/yosys into dff_init
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2019-02-17
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-02-13
Eddie Hung
Merge remote-tracking branch 'origin/read_aiger' into...
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2019-02-13
Eddie Hung
Merge https://github.com/YosysHQ/yosys into xaig
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2019-02-08
Eddie Hung
Merge remote-tracking branch 'origin/dff_init' into...
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2019-02-06
Eddie Hung
Cope WIDTH of ff/latch cells is default of zero
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2019-02-06
Eddie Hung
Merge branch 'dff_init' of https://github.com/eddiehung...
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2019-02-06
Eddie Hung
Add INIT parameter to all ff/latch cells
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2018-02-23
Clifford Wolf
Merge branch 'forall'
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2018-02-23
Clifford Wolf
Add $allconst and $allseq cell types
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2017-02-25
Clifford Wolf
Merge branch 'master' of https://github.com/klammerj...
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2017-02-25
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-02-25
Clifford Wolf
Add $live and $fair cell types, add support for s_event...
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2017-02-11
Clifford Wolf
Merge branch 'master' of https://github.com/stv0g/yosys...
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2017-02-09
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2017-02-04
Clifford Wolf
Add $cover cell type and SVA cover() support
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2016-10-14
Clifford Wolf
Added $anyseq cell type
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2016-10-14
Clifford Wolf
Added $global_clock verilog syntax support for creating...
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2016-10-11
Clifford Wolf
Added $ff and $_FF_ cell types
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2016-08-30
Clifford Wolf
Removed $aconst cell type
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2016-08-28
Clifford Wolf
Removed $predict again
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2016-07-30
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-07-27
Clifford Wolf
Added $anyconst and $aconst
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2016-07-21
Clifford Wolf
Added $initstate cell type and vlog function
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2016-07-21
Clifford Wolf
After reading the SV spec, using non-standard predict...
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2016-07-13
Clifford Wolf
Added basic support for $expect cells
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-06-17
Clifford Wolf
Improved support for $sop cells
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2016-06-17
Clifford Wolf
Added $sop cell type and "abc -sop"
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2016-03-30
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-03-29
Clifford Wolf
Added more cell help messages
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-09-25
Clifford Wolf
Added read-enable to memory model
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2015-08-16
Clifford Wolf
Added $tribuf and $_TBUF_ sim models
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2015-08-14
Larry Doolittle
Another block of spelling fixes
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2015-07-31
Clifford Wolf
Added WORDS parameter to $meminit
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-04-05
Clifford Wolf
make all vector-size related integer params in $mem...
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2015-02-26
Clifford Wolf
Added $assume cell type
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2015-02-14
Clifford Wolf
Smaller default parameters in $mem simlib model
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2015-02-14
Clifford Wolf
Added $meminit support to "memory" command
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2015-02-14
Clifford Wolf
Added $meminit cell type
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2015-02-12
Clifford Wolf
Some test related fixes
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2015-01-19
Clifford Wolf
Added $equiv cell type
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2015-01-03
Clifford Wolf
Progress in memory_bram
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2015-01-02
Clifford Wolf
Added proper clkpol support to memory_bram
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2015-01-02
Clifford Wolf
New $mem simlib model
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2014-12-30
Clifford Wolf
Fixed simlib entries for $memrd and $memwr
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2014-12-08
Clifford Wolf
Added $dffe cell type
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-09-16
Clifford Wolf
Fixed $macc simlib model for zero-config
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2014-09-08
Clifford Wolf
Fixed simlib $macc model for xilinx xsim
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2014-09-08
Clifford Wolf
Simplified $fa undef model
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2014-09-08
Clifford Wolf
Fixes and cleanups for blackbox.v
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2014-09-08
Clifford Wolf
Added $lcu cell type
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2014-09-08
Clifford Wolf
Added "$fa" cell type
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2014-09-06
Clifford Wolf
Various bug fixes (related to $macc model testing)
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2014-09-06
Clifford Wolf
Added $macc SAT model
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2014-09-06
Clifford Wolf
Added $macc simlib model (also use as techmap rule...
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2014-09-04
Clifford Wolf
Removed $bu0 cell type
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2014-09-02
Clifford Wolf
Undef-related fixes in simlib $alu model
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2014-09-02
Clifford Wolf
Small bug fixes in $not, $neg, and $shiftx models
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2014-09-01
Clifford Wolf
Fixed "test_cell -simlib all"
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2014-08-30
Clifford Wolf
Added $alu cell type
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2014-08-15
Clifford Wolf
Renamed $lut ports to follow A-Y naming scheme
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2014-08-14
Clifford Wolf
RIP $safe_pmux
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2014-07-29
Clifford Wolf
Bugfix in simlib.v for iverilog
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2014-07-29
Clifford Wolf
Added $shift and $shiftx cell types (needed for correct...
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2014-07-17
Clifford Wolf
Fixed simlib.v model for $mem
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2014-07-16
Clifford Wolf
Merged new $mem/$memwr WR_EN interface
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2014-07-16
Clifford Wolf
Updated simlib to new $mem/$memwr interface
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2014-04-02
Clifford Wolf
Added SIMLIB_NOLUT to simlib.v
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2014-04-02
Clifford Wolf
Added SIMLIB_NOSR to simlib.v
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2014-03-31
Clifford Wolf
Added support for dlatchsr cells
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2014-02-07
Clifford Wolf
Added $slice and $concat cell types
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2014-02-03
Clifford Wolf
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
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2014-01-31
Clifford Wolf
More changes to techlibs/common/simlib.v for LEC
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2014-01-28
Clifford Wolf
Major rewrite of techlibs/common/simlib.v for LEC ...
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2014-01-20
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-19
Clifford Wolf
Added $assert cell
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2014-01-18
Clifford Wolf
Fixed $lut simlib model for a wider range of tools
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2014-01-18
Clifford Wolf
More changes to simlib to make it friendlier to a wider...
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2014-01-18
Clifford Wolf
Fixed a type in $mem model in simlib.v
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2014-01-18
Ahmed Irfan
Merge branch 'master' of https://github.com/ahmedirfan1...
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