Add (* abc_flop_q *) to brams_bb.v
[yosys.git] / techlibs / common / simlib.v
2019-05-31 Eddie HungMerge branch 'xaig' into xc7mux
2019-05-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-05-21 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-05-08 Clifford WolfMerge pull request #991 from kristofferkoch/gcc9-warnings
2019-05-06 Clifford WolfMerge pull request #946 from YosysHQ/clifford/specify
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-05-03 Eddie HungMerge remote-tracking branch 'origin/master' into cliff...
2019-04-23 Clifford WolfImprove $specrule interface
2019-04-23 Clifford WolfImprove $specrule interface
2019-04-23 Clifford WolfAdd $specrule cells for $setup/$hold/$skew specify...
2019-04-23 Clifford WolfRename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better...
2019-04-23 Clifford WolfAdd $specify2 and $specify3 cells to simlib
2019-02-19 Eddie HungMerge branch 'master' into xaig
2019-02-19 Eddie HungMerge branch 'master' into read_aiger
2019-02-18 Eddie HungMerge branch 'dff_init' into read_aiger
2019-02-17 Eddie HungRevert "Add INIT parameter to all ff/latch cells"
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-02-13 Eddie HungMerge remote-tracking branch 'origin/read_aiger' into...
2019-02-13 Eddie HungMerge https://github.com/YosysHQ/yosys into xaig
2019-02-08 Eddie HungMerge remote-tracking branch 'origin/dff_init' into...
2019-02-06 Eddie HungCope WIDTH of ff/latch cells is default of zero
2019-02-06 Eddie HungMerge branch 'dff_init' of https://github.com/eddiehung...
2019-02-06 Eddie HungAdd INIT parameter to all ff/latch cells
2018-02-23 Clifford WolfMerge branch 'forall'
2018-02-23 Clifford WolfAdd $allconst and $allseq cell types
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj...
2017-02-25 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 Clifford WolfAdd $live and $fair cell types, add support for s_event...
2017-02-11 Clifford WolfMerge branch 'master' of https://github.com/stv0g/yosys...
2017-02-09 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-04 Clifford WolfAdd $cover cell type and SVA cover() support
2016-10-14 Clifford WolfAdded $anyseq cell type
2016-10-14 Clifford WolfAdded $global_clock verilog syntax support for creating...
2016-10-11 Clifford WolfAdded $ff and $_FF_ cell types
2016-08-30 Clifford WolfRemoved $aconst cell type
2016-08-28 Clifford WolfRemoved $predict again
2016-07-30 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-07-27 Clifford WolfAdded $anyconst and $aconst
2016-07-21 Clifford WolfAdded $initstate cell type and vlog function
2016-07-21 Clifford WolfAfter reading the SV spec, using non-standard predict...
2016-07-13 Clifford WolfAdded basic support for $expect cells
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-06-17 Clifford WolfImproved support for $sop cells
2016-06-17 Clifford WolfAdded $sop cell type and "abc -sop"
2016-03-30 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-03-29 Clifford WolfAdded more cell help messages
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-09-25 Clifford WolfAdded read-enable to memory model
2015-08-16 Clifford WolfAdded $tribuf and $_TBUF_ sim models
2015-08-14 Larry DoolittleAnother block of spelling fixes
2015-07-31 Clifford WolfAdded WORDS parameter to $meminit
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-05 Clifford Wolfmake all vector-size related integer params in $mem...
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-26 Clifford WolfAdded $assume cell type
2015-02-14 Clifford WolfSmaller default parameters in $mem simlib model
2015-02-14 Clifford WolfAdded $meminit support to "memory" command
2015-02-14 Clifford WolfAdded $meminit cell type
2015-02-12 Clifford WolfSome test related fixes
2015-01-19 Clifford WolfAdded $equiv cell type
2015-01-03 Clifford WolfProgress in memory_bram
2015-01-02 Clifford WolfAdded proper clkpol support to memory_bram
2015-01-02 Clifford WolfNew $mem simlib model
2014-12-30 Clifford WolfFixed simlib entries for $memrd and $memwr
2014-12-08 Clifford WolfAdded $dffe cell type
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-09-16 Clifford WolfFixed $macc simlib model for zero-config
2014-09-08 Clifford WolfFixed simlib $macc model for xilinx xsim
2014-09-08 Clifford WolfSimplified $fa undef model
2014-09-08 Clifford WolfFixes and cleanups for blackbox.v
2014-09-08 Clifford WolfAdded $lcu cell type
2014-09-08 Clifford WolfAdded "$fa" cell type
2014-09-06 Clifford WolfVarious bug fixes (related to $macc model testing)
2014-09-06 Clifford WolfAdded $macc SAT model
2014-09-06 Clifford WolfAdded $macc simlib model (also use as techmap rule...
2014-09-04 Clifford WolfRemoved $bu0 cell type
2014-09-02 Clifford WolfUndef-related fixes in simlib $alu model
2014-09-02 Clifford WolfSmall bug fixes in $not, $neg, and $shiftx models
2014-09-01 Clifford WolfFixed "test_cell -simlib all"
2014-08-30 Clifford WolfAdded $alu cell type
2014-08-15 Clifford WolfRenamed $lut ports to follow A-Y naming scheme
2014-08-14 Clifford WolfRIP $safe_pmux
2014-07-29 Clifford WolfBugfix in simlib.v for iverilog
2014-07-29 Clifford WolfAdded $shift and $shiftx cell types (needed for correct...
2014-07-17 Clifford WolfFixed simlib.v model for $mem
2014-07-16 Clifford WolfMerged new $mem/$memwr WR_EN interface
2014-07-16 Clifford WolfUpdated simlib to new $mem/$memwr interface
2014-04-02 Clifford WolfAdded SIMLIB_NOLUT to simlib.v
2014-04-02 Clifford WolfAdded SIMLIB_NOSR to simlib.v
2014-03-31 Clifford WolfAdded support for dlatchsr cells
2014-02-07 Clifford WolfAdded $slice and $concat cell types
2014-02-03 Clifford WolfAdded TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
2014-01-31 Clifford WolfMore changes to techlibs/common/simlib.v for LEC
2014-01-28 Clifford WolfMajor rewrite of techlibs/common/simlib.v for LEC ...
2014-01-20 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-19 Clifford WolfAdded $assert cell
2014-01-18 Clifford WolfFixed $lut simlib model for a wider range of tools
2014-01-18 Clifford WolfMore changes to simlib to make it friendlier to a wider...
2014-01-18 Clifford WolfFixed a type in $mem model in simlib.v
next