Techmap flops before ABC again
[yosys.git] / techlibs / ecp5 / arith_map.v
2019-04-08 Eddie HungMerge branch 'master' into xaig
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-01 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-03-01 Clifford WolfMerge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
2019-02-28 Clifford WolfMerge pull request #794 from daveshah1/ecp5improve
2019-01-21 David Shahecp5: Increase threshold for ALU mapping
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-08-15 Clifford WolfMerge pull request #562 from udif/pr_fix_illegal_port_decl
2018-07-18 Aman GoelMerge pull request #2 from YosysHQ/master
2018-07-16 Clifford WolfMerge pull request #581 from daveshah1/ecp5
2018-07-16 David Shahecp5: ECP5 synthesis fixes
2018-07-13 David Shahecp5: Cells and mappings fixes
2018-07-13 David Shahecp5: Fixing arith_map
2018-07-13 David Shahecp5: Initial arith_map implementation