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Update synth_ice40 -device doc to be relevant for -abc9 only
[yosys.git]
/
techlibs
/
ecp5
/
cells_sim.v
2019-06-28
Eddie Hung
Disable boxing of ECP5 dist RAM due to regression
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2019-06-28
Eddie Hung
Add write address to abc_scc_break of ECP5 dist RAM
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2019-06-27
Eddie Hung
Refactor for one "abc_carry" attribute on module
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2019-06-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-27
Eddie Hung
Merge origin/master
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2019-06-27
Eddie Hung
Merge pull request #1138 from YosysHQ/koriakin/xc7nocar...
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2019-06-27
Eddie Hung
Add WE to ECP5 dist RAM's abc_scc_break too
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2019-06-26
Eddie Hung
Merge branch 'koriakin/xc7nocarrymux' into xaig
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2019-06-26
Eddie Hung
Merge branch 'koriakin/xc7nocarrymux' into xaig
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2019-06-26
Eddie Hung
Merge branch 'koriakin/xc7nocarrymux' into xaig
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2019-06-26
Clifford Wolf
Merge pull request #1137 from mmicko/cell_sim_fix
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2019-06-26
Eddie Hung
Merge branch 'koriakin/xc7nocarrymux' into xaig
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2019-06-26
Miodrag Milanovic
Simulation model verilog fix
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2019-06-26
whitequark
Add more ECP5 Diamond flip-flops.
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2019-06-25
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-25
Eddie Hung
Re-enable dist RAM boxes for ECP5
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2019-06-25
Eddie Hung
Revert "Re-enable dist RAM boxes for ECP5"
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2019-06-25
Eddie Hung
Re-enable dist RAM boxes for ECP5
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2019-06-25
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-22
Eddie Hung
Merge branch 'master' into xaig
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2019-06-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-14
Eddie Hung
Comment out dist RAM boxing on ECP5 for now
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2019-06-14
Eddie Hung
Remove WIP ABC9 flop support
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2019-06-14
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-06-14
Eddie Hung
Merge branch 'xaig' of github.com:YosysHQ/yosys into...
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2019-06-14
Eddie Hung
Merge pull request #1097 from YosysHQ/dave/xaig_ecp5
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2019-06-14
David Shah
ecp5: Add abc9 option
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2019-06-13
Serge Bazanski
Merge pull request #829 from abdelrahmanhosny/master
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2019-04-08
Eddie Hung
Merge branch 'master' into xaig
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2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2019-03-19
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-03-14
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-09
Clifford Wolf
Merge pull request #859 from smunaut/ice40_braminit
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2019-03-04
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-03-01
Clifford Wolf
Merge pull request #841 from mmicko/master
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2019-03-01
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-03-01
Miodrag Milanovic
Fix ECP5 cells_sim for iverilog
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2019-03-01
Clifford Wolf
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
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2019-02-28
Clifford Wolf
Merge pull request #794 from daveshah1/ecp5improve
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2019-02-28
Clifford Wolf
Merge pull request #827 from ucb-bar/firrtlfixes
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2019-02-26
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig
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2019-02-26
Larry Doolittle
Clean up some whitepsace outliers
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2019-02-25
David Shah
ecp5: Compatibility with Migen AsyncResetSynchronizer
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2019-01-21
David Shah
ecp5: Add LSRMODE to flipflops for PRLD support
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2018-12-18
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2018-12-01
Clifford Wolf
Merge pull request #676 from rafaeltp/master
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2018-11-12
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys
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2018-11-12
Clifford Wolf
Merge pull request #697 from eddiehung/xilinx_ps7
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2018-11-12
Clifford Wolf
Merge pull request #695 from daveshah1/ecp5_bb
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2018-11-07
David Shah
ecp5: Adding some blackbox cells
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2018-10-21
rafaeltp
Merge pull request #1 from YosysHQ/master
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2018-10-19
Clifford Wolf
Merge pull request #673 from daveshah1/ecp5_improve
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2018-10-19
David Shah
ecp5: Sim model fixes
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2018-10-19
Clifford Wolf
Merge pull request #672 from daveshah1/fix_bram
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2018-10-18
Clifford Wolf
Merge pull request #659 from rubund/sv_interfaces
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2018-10-18
Clifford Wolf
Merge pull request #657 from mithro/xilinx-vpr
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2018-10-18
Clifford Wolf
Merge pull request #664 from tklam/ignore-verilog-protect
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2018-10-17
Clifford Wolf
Merge pull request #660 from tklam/parse-liberty-detect...
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2018-10-17
Clifford Wolf
Merge pull request #663 from aman-goel/master
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2018-10-17
Clifford Wolf
Merge pull request #658 from daveshah1/ecp5_bram
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2018-10-10
David Shah
ecp5: First BRAM type maps successfully
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2018-10-10
David Shah
ecp5: Script for BRAM IO connections
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2018-10-09
David Shah
ecp5: Adding BRAM initialisation and config
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2018-10-05
David Shah
ecp5: Add blackbox for DP16KD
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #576 from cr1901/no-resource
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2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
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2018-08-15
Clifford Wolf
Merge pull request #562 from udif/pr_fix_illegal_port_decl
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2018-07-18
Aman Goel
Merge pull request #2 from YosysHQ/master
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2018-07-16
Clifford Wolf
Merge pull request #581 from daveshah1/ecp5
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2018-07-16
David Shah
ecp5: Fixing miscellaneous sim model issues
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2018-07-16
David Shah
ecp5: Fixing 'X' issues with LUT simulation models
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2018-07-16
David Shah
ecp5: ECP5 synthesis fixes
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2018-07-13
David Shah
ecp5: Cells and mappings fixes
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2018-07-13
David Shah
ecp5: Adding DFF maps
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2018-07-13
David Shah
ecp5: Adding DRAM map
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2018-07-13
David Shah
ecp5: Adding basic cells_sim and mapper for LUTs up...
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