Merge pull request #1160 from ZirconiumX/cyclone_v
[yosys.git] / techlibs / ecp5 /
2019-02-22 Clifford WolfMerge pull request #740 from daveshah1/improve_dress
2019-02-19 David Shahecp5: Add DDRDLLA
2019-02-19 David Shahecp5: Add DELAYF/DELAYG blackboxes
2019-02-13 David Shahecp5: Add ECLKSYNCB blackbox
2019-02-12 David Shahecp5: Full set of IO-related blackboxes
2019-02-11 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-02-06 David Shahecp5: Use abc -dress
2019-01-22 David Shahecp5: Support for flipflop initialisation
2019-01-21 David Shahecp5: Add LSRMODE to flipflops for PRLD support
2019-01-21 David Shahecp5: More blackboxes
2019-01-21 David Shahecp5: Increase threshold for ALU mapping
2019-01-02 Clifford WolfMerge pull request #770 from whitequark/opt_expr_cmp
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init
2019-01-02 Clifford WolfMerge pull request #773 from whitequark/opt_lut_elim_fixes
2019-01-02 Clifford WolfMerge pull request #772 from whitequark/synth_lut
2019-01-02 Clifford WolfMerge pull request #771 from whitequark/techmap_cmp2lut
2019-01-02 Clifford WolfMerge pull request #769 from whitequark/typos
2019-01-02 whitequarkFix typographical and grammatical errors and inconsiste...
2018-12-31 Clifford WolfMerge pull request #766 from Icenowy/anlogic-latches
2018-12-29 Larry DoolittleFix 7 instances of add_share_file to add_gen_share_file
2018-12-18 Jim LawsonMerge remote-tracking branch 'upstream/master'
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master
2018-11-12 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys
2018-11-12 Clifford WolfMerge pull request #697 from eddiehung/xilinx_ps7
2018-11-12 Clifford WolfMerge pull request #695 from daveshah1/ecp5_bb
2018-11-09 David Shahecp5: Add 'fake' DCU parameters
2018-11-09 David Shahecp5: Add blackboxes for ancillary DCU cells
2018-11-07 David Shahecp5: Adding some blackbox cells
2018-10-25 Clifford WolfMerge pull request #678 from whentze/master
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp
2018-10-22 David Shahecp5: Remove DSP parameters that don't work
2018-10-21 David Shahecp5: Add DSP blackboxes
2018-10-21 rafaeltpMerge pull request #1 from YosysHQ/master
2018-10-19 Clifford WolfMerge pull request #673 from daveshah1/ecp5_improve
2018-10-19 David Shahecp5: Sim model fixes
2018-10-19 David Shahecp5: Add latch inference
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces
2018-10-18 Clifford WolfMerge pull request #657 from mithro/xilinx-vpr
2018-10-18 Clifford WolfMerge pull request #664 from tklam/ignore-verilog-protect
2018-10-17 Clifford WolfMerge pull request #660 from tklam/parse-liberty-detect...
2018-10-17 Clifford WolfMerge pull request #663 from aman-goel/master
2018-10-17 Clifford WolfMerge pull request #658 from daveshah1/ecp5_bram
2018-10-17 Clifford WolfMerge pull request #638 from udif/pr_reg_wire_error
2018-10-16 Clifford WolfMerge branch 'yosys-0.8-rc'
2018-10-16 David Shahecp5: Disable LSR inversion
2018-10-12 David ShahBRAM improvements
2018-10-10 David Shahecp5: Adding BRAM maps for all size options
2018-10-10 David Shahecp5: First BRAM type maps successfully
2018-10-10 David Shahecp5: Script for BRAM IO connections
2018-10-09 David Shahecp5: Adding BRAM initialisation and config
2018-10-08 David Shahecp5: Don't map ROMs to DRAM
2018-10-05 David Shahecp5: Add blackbox for DP16KD
2018-10-05 Clifford WolfMerge pull request #651 from ARandomOWL/stdcells_fix
2018-10-03 tklamMerge branch 'master' of https://github.com/YosysHQ...
2018-10-02 Clifford WolfMerge pull request #645 from daveshah1/ecp5_dram_fix
2018-10-01 David Shahecp5: Don't map ROMs to DRAM
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-08-15 Clifford WolfMerge pull request #562 from udif/pr_fix_illegal_port_decl
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2018-07-18 Aman GoelMerge pull request #2 from YosysHQ/master
2018-07-16 Clifford WolfMerge pull request #581 from daveshah1/ecp5
2018-07-16 David Shahecp5: Fixing miscellaneous sim model issues
2018-07-16 David Shahecp5: Fixing 'X' issues with LUT simulation models
2018-07-16 David Shahecp5: ECP5 synthesis fixes
2018-07-14 David Shahecp5: Adding synchronous set/reset support
2018-07-13 David Shahecp5: Add DRAM match rule
2018-07-13 David Shahecp5: Cells and mappings fixes
2018-07-13 David Shahecp5: Fixing arith_map
2018-07-13 David Shahecp5: Initial arith_map implementation
2018-07-13 David Shahecp5: Adding basic synth_ecp5 based on synth_ice40
2018-07-13 David Shahecp5: Adding DFF maps
2018-07-13 David Shahecp5: Adding DRAM map
2018-07-13 David Shahecp5: Adding basic cells_sim and mapper for LUTs up...