projects / yosys.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
[yosys.git] / techlibs / ecp5 /
2018-10-16 David Shahecp5: Disable LSR inversion tree | commitdiff
2018-10-12 David ShahBRAM improvements tree | commitdiff
2018-10-10 David Shahecp5: Adding BRAM maps for all size options tree | commitdiff
2018-10-10 David Shahecp5: First BRAM type maps successfully tree | commitdiff
2018-10-10 David Shahecp5: Script for BRAM IO connections tree | commitdiff
2018-10-09 David Shahecp5: Adding BRAM initialisation and config tree | commitdiff
2018-10-08 David Shahecp5: Don't map ROMs to DRAM tree | commitdiff
2018-10-05 David Shahecp5: Add blackbox for DP16KD tree | commitdiff
2018-10-05 Clifford WolfMerge pull request #651 from ARandomOWL/stdcells_fix tree | commitdiff
2018-10-03 tklamMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2018-10-02 Clifford WolfMerge pull request #645 from daveshah1/ecp5_dram_fix tree | commitdiff
2018-10-01 David Shahecp5: Don't map ROMs to DRAM tree | commitdiff
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error tree | commitdiff
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master tree | commitdiff
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64 tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #562 from udif/pr_fix_illegal_port_decl tree | commitdiff
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in... tree | commitdiff
2018-07-18 Aman GoelMerge pull request #2 from YosysHQ/master tree | commitdiff
2018-07-16 Clifford WolfMerge pull request #581 from daveshah1/ecp5 tree | commitdiff
2018-07-16 David Shahecp5: Fixing miscellaneous sim model issues tree | commitdiff
2018-07-16 David Shahecp5: Fixing 'X' issues with LUT simulation models tree | commitdiff
2018-07-16 David Shahecp5: ECP5 synthesis fixes tree | commitdiff
2018-07-14 David Shahecp5: Adding synchronous set/reset support tree | commitdiff
2018-07-13 David Shahecp5: Add DRAM match rule tree | commitdiff
2018-07-13 David Shahecp5: Cells and mappings fixes tree | commitdiff
2018-07-13 David Shahecp5: Fixing arith_map tree | commitdiff
2018-07-13 David Shahecp5: Initial arith_map implementation tree | commitdiff
2018-07-13 David Shahecp5: Adding basic synth_ecp5 based on synth_ice40 tree | commitdiff
2018-07-13 David Shahecp5: Adding DFF maps tree | commitdiff
2018-07-13 David Shahecp5: Adding DRAM map tree | commitdiff
2018-07-13 David Shahecp5: Adding basic cells_sim and mapper for LUTs up... tree | commitdiff