Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
[yosys.git] / techlibs / efinix /
2019-09-18 Eddie HungMerge pull request #1355 from YosysHQ/eddie/peepopt_dff...
2019-09-18 Eddie HungMerge pull request #1379 from mmicko/sim_models
2019-09-18 Miodrag Milanovicbetter handling of lut and begin/end add
2019-09-15 Miodrag MilanovicAdded simulation models for Efinix and Anlogic
2019-08-29 SergeyMerge pull request #3 from YosysHQ/Sergey/tests_ice40
2019-08-28 Eddie HungMerge remote-tracking branch 'origin/clifford/async2syn...
2019-08-26 Clifford WolfMerge tag 'yosys-0.9'
2019-08-25 Clifford WolfMerge pull request #1112 from acw1251/pyosys_sigsig_issue
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_...
2019-08-23 Eddie HungMerge remote-tracking branch 'origin/master' into mwk...
2019-08-22 Eddie HungMerge pull request #1319 from TeaEngineering/shuckc...
2019-08-22 Eddie HungMerge remote-tracking branch 'origin/master' into eddie...
2019-08-22 Eddie HungMerge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx
2019-08-22 Clifford WolfMerge pull request #1289 from mmicko/anlogic_fixes
2019-08-22 Clifford WolfFix missing newline at end of file
2019-08-22 Clifford WolfMerge pull request #1281 from mmicko/efinix
2019-08-11 Miodrag MilanovicFix formating
2019-08-11 Miodrag Milanovicone bit enable signal
2019-08-11 Miodrag Milanovicfix mixing signals on FF mapping
2019-08-11 Miodrag MilanovicReplaced custom step with setundef
2019-08-11 Miodrag MilanovicFixed data width
2019-08-11 Miodrag MilanovicAdding new pass to fix carry chain
2019-08-11 Miodrag Milanoviccleanup
2019-08-09 Miodrag MilanovicFix CO
2019-08-09 Miodrag MilanovicMerge remote-tracking branch 'upstream/master' into...
2019-08-04 Miodrag Milanovicclock for ram trough gbuf
2019-08-04 Miodrag MilanovicAdded bram support
2019-08-03 Miodrag MilanovicCustom step to add global clock buffers
2019-08-03 Miodrag MilanovicInitial EFINIX support