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Remove peepopt call in synth_xilinx since already in synth -run coarse
[yosys.git]
/
techlibs
/
ice40
/
brams_map.v
2019-06-13
Serge Bazanski
Merge pull request #829 from abdelrahmanhosny/master
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2019-04-08
Eddie Hung
Merge branch 'master' into xaig
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2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2019-03-19
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-03-14
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-09
Clifford Wolf
Merge pull request #859 from smunaut/ice40_braminit
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2019-03-01
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-03-01
Clifford Wolf
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
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2019-03-01
Elms
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-11-24
Clifford Wolf
Fixed WE/RE usage in iCE40 BRAM mapping
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2015-09-25
Clifford Wolf
Added read-enable to memory model
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2015-09-10
Clifford Wolf
Fixed ice40 handling of negclk RAM40
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2015-04-26
Clifford Wolf
Initialization support for all iCE40 bram modes
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2015-04-25
Clifford Wolf
initialized iCE40 brams (mode 0)
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2015-04-25
Clifford Wolf
More iCE40 bram improvements
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2015-04-24
Clifford Wolf
iCE40 bram progress
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2015-04-24
Clifford Wolf
iCE40 bram tests and fixes
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2015-04-23
Clifford Wolf
Added ice40 bram support
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