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Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
[yosys.git]
/
techlibs
/
intel
/
cycloneive
/
2019-06-13
Serge Bazanski
Merge pull request #829 from abdelrahmanhosny/master
tree
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commitdiff
2019-04-08
Eddie Hung
Merge branch 'master' into xaig
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commitdiff
2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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commitdiff
2019-03-19
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-03-14
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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commitdiff
2019-03-09
Clifford Wolf
Merge pull request #859 from smunaut/ice40_braminit
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commitdiff
2019-03-01
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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commitdiff
2019-03-01
Clifford Wolf
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
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commitdiff
2019-02-28
Larry Doolittle
Reduce amount of trailing whitespace in code base
tree
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commitdiff
2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
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commitdiff
2018-04-01
Clifford Wolf
Merge pull request #522 from c60k28/master
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commitdiff
2018-04-01
c60k28
Fixed broken Quartus backend on dffeas init value ...
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2017-10-10
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2017-10-05
Larry Doolittle
Clean whitespace and permissions in techlibs/intel
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2017-10-03
Clifford Wolf
Merge branch 'pr_ast_const_funcs' of https://github...
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2017-10-03
Clifford Wolf
Merge branch 'fix_shift_reduce_conflict' of https:...
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2017-10-03
Clifford Wolf
Merge branch 'dh73-master'
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2017-10-01
dh73
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and...
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