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Remove peepopt call in synth_xilinx since already in synth -run coarse
[yosys.git]
/
techlibs
/
intel
/
max10
/
2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
tree
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commitdiff
2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
tree
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commitdiff
2018-04-01
Clifford Wolf
Merge pull request #522 from c60k28/master
tree
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commitdiff
2018-04-01
c60k28
Fixed broken Quartus backend on dffeas init value ...
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commitdiff
2017-10-10
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
tree
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commitdiff
2017-10-05
Larry Doolittle
Clean whitespace and permissions in techlibs/intel
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commitdiff
2017-10-03
Clifford Wolf
Merge branch 'pr_ast_const_funcs' of https://github...
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commitdiff
2017-10-03
Clifford Wolf
Merge branch 'fix_shift_reduce_conflict' of https:...
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commitdiff
2017-10-03
Clifford Wolf
Merge branch 'dh73-master'
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commitdiff
2017-10-01
dh73
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and...
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commitdiff