Muck about with LUT delays some more
[yosys.git] / techlibs / xilinx / Makefile.inc
2019-05-26 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-05-23 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-05-23 Eddie HungMerge remote-tracking branch 'origin/eddie/opt_rmdff...
2019-05-21 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-05-02 Eddie HungMerge remote-tracking branch 'origin/clifford/pmgenstuf...
2019-05-02 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-04-26 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-04-26 Eddie HungMerge remote-tracking branch 'origin/eddie/split_shiftx...
2019-04-26 Eddie HungMerge branch 'eddie/split_shiftx' into xc7mux
2019-04-22 Eddie HungCleanup, call pmux2shiftx even without -nosrl
2019-04-22 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/xc7srl' into xc7mux
2019-04-16 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-16 Eddie HungAdd +/xilinx/cells_box.v containing models for ABC...
2019-04-16 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-12 Eddie HungMerge remote-tracking branch 'origin/master' into xc7mux
2019-04-11 Eddie HungMerge remote-tracking branch 'origin/pmux2shiftx' into...
2019-04-11 Eddie HungMerge remote-tracking branch 'origin/pmux2shiftx' into...
2019-04-11 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-10 Eddie HungMerge branch 'xaig' into xc7mux
2019-04-09 Eddie HungAdd cells.lut to techlibs/xilinx/
2019-04-09 Eddie HungAdd techlibs/xilinx/cells.box
2019-04-08 Eddie HungMerge branch 'master' into xaig
2019-04-01 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-05 Clifford WolfMerge pull request #842 from litghost/merge_upstream
2019-03-01 Keith RothmanChanges required for VPR place and route synth_xilinx.
2018-03-07 Clifford WolfAdd Xilinx RAM64X1D and RAM128X1D simulation models
2017-07-10 Clifford WolfAdd techlibs/xilinx/lut2lut.v
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-03-19 Clifford WolfAdded black box modules for all the 7-series design...
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-08-22 Clifford WolfSwitched to Python 3
2015-08-16 Clifford WolfAnother bugfix for ice40 and xilinx brams_init make...
2015-08-16 Clifford WolfFixed Makefile rules for generated share files
2015-08-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-08-12 Clifford WolfAdjust makefiles to work with out-of-tree builds
2015-05-17 Clifford WolfVerific build fixes
2015-04-09 Clifford WolfTowards DRAM support in Xilinx flow
2015-04-06 Clifford WolfAdded support for initialized xilinx brams
2015-04-06 Clifford WolfAdded Xilinx bram black-box modules
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-01-18 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-01-18 Clifford WolfVarious cleanups in xilinx techlib
2015-01-17 Clifford WolfAdded MUXCY and XORCY support to synth_xilinx
2015-01-07 Clifford WolfAdded add_share_file Makefile macro
2015-01-04 Clifford WolfTowards Xilinx bram support
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-07-24 Clifford WolfAdded "make PRETTY=1"
2013-10-27 Clifford WolfAdded synth_xilinx command