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Merge remote-tracking branch 'origin/master' into xaig_dff
[yosys.git]
/
techlibs
/
xilinx
/
abc9_map.v
2019-12-20
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-12-20
Eddie Hung
Add RAM{32,64}M to abc9_map.v
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2019-12-19
Eddie Hung
Add RAM{32,64}M to abc9_map.v
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2019-12-19
Eddie Hung
Split into $__ABC9_ASYNC[01], do not add cell->type...
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2019-12-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-12-19
Eddie Hung
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
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2019-12-19
Eddie Hung
Merge pull request #1569 from YosysHQ/eddie/fix_1531
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2019-12-19
Eddie Hung
Merge pull request #1571 from YosysHQ/eddie/fix_1570
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2019-12-18
David Shah
Merge pull request #1563 from YosysHQ/dave/async-prld
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2019-12-18
Eddie Hung
Merge pull request #1572 from nakengelhardt/scratchpad_pass
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2019-12-16
Eddie Hung
Merge pull request #1577 from gromero/for-yosys
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2019-12-13
Eddie Hung
Merge pull request #1533 from dh73/bram_xilinx
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2019-12-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-12-12
Eddie Hung
abc9_map.v: fix Xilinx LUTRAM
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2019-12-12
Eddie Hung
abc9_map.v: fix Xilinx LUTRAM
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2019-12-07
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-12-07
Eddie Hung
Remove creation of $abc9_control_wire
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2019-12-06
Eddie Hung
abc9 to use mergeability class to differentiate sync...
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2019-12-05
Eddie Hung
Revert "Special abc9_clock wire to contain only clock...
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2019-12-05
Eddie Hung
Missing wire declaration
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2019-12-05
Eddie Hung
abc9_map.v to transform INIT=1 to INIT=0
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2019-12-05
Eddie Hung
output reg Q -> output Q to suppress warning
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2019-12-05
Eddie Hung
abc9_map.v to do `zinit' and make INIT = 1'b0
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2019-12-04
Eddie Hung
Add abc9_init wire, attach to abc9_flop cell
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2019-12-03
Eddie Hung
Revert "Add INIT value to abc9_control"
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2019-12-02
Eddie Hung
Add INIT value to abc9_control
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2019-11-28
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/write_xaiger...
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2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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2019-11-27
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-27
Eddie Hung
Merge branch 'master' into xaig_dff
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2019-11-25
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-11-25
Eddie Hung
Special abc9_clock wire to contain only clock signal
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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2019-11-23
Eddie Hung
Merge pull request #1505 from YosysHQ/eddie/xaig_dff_adff
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/clkpart...
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2019-11-23
Eddie Hung
Merge remote-tracking branch 'origin/eddie/submod_po...
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2019-11-22
Eddie Hung
Merge branch 'eddie/clkpart' into xaig_dff
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2019-11-22
Eddie Hung
Merge branch 'eddie/clkpart' into xaig_dff
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2019-11-22
Eddie Hung
Merge branch 'master' of github.com:YosysHQ/yosys
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2019-11-22
Eddie Hung
Merge remote-tracking branch 'origin/xaig_dff' into...
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2019-11-22
Eddie Hung
Merge branch 'eddie/xaig_dff_adff' into xaig_dff
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2019-11-20
Eddie Hung
Fix INIT values
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2019-11-20
Eddie Hung
Do not drop async control signals in abc_map.v
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2019-11-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-10-27
Clifford Wolf
Merge pull request #1393 from whitequark/write_verilog...
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2019-10-21
Pepijn de Vos
Merge branch 'master' of https://github.com/YosysHQ...
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2019-10-18
Miodrag Milanović
Merge branch 'master' into mmicko/efinix
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2019-10-18
Miodrag Milanović
Merge branch 'master' into mmicko/anlogic
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2019-10-18
Miodrag Milanović
Merge branch 'master' into eddie/pr1352
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2019-10-14
Clifford Wolf
Use "(id)" instead of "id" for types as temporary hack
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2019-10-08
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-10-08
Eddie Hung
Merge pull request #1432 from YosysHQ/eddie/fix1427
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2019-10-08
Eddie Hung
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_a...
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2019-10-08
Eddie Hung
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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2019-10-07
Eddie Hung
Cleanup
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2019-10-07
Eddie Hung
Rename $currQ to $abc9_currQ
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2019-10-07
Eddie Hung
Update comments in abc9_map.v
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2019-10-06
Eddie Hung
Do not require changes to cells_sim.v; try and work...
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2019-10-05
Eddie Hung
Merge branch 'master' into eddie/abc_to_abc9
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2019-10-05
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-10-05
Eddie Hung
Fix merge issues
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2019-10-04
Eddie Hung
Merge remote-tracking branch 'origin/eddie/abc_to_abc9...
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2019-10-04
Eddie Hung
Rename abc_* names/attributes to more precisely be...
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